System For Decoding Coded Data With PLL

ABSTRACT

A system for decoding coded data printed in ink on a surface is provided. The coded data has a registration structure which has at least two clock tracks indicative of a position of the coded data in the direction perpendicular to an alignment direction and two alignment lines for each clock track. The two alignment lines are indicative of the position of the respective clock track. The system has a decoder for determining, using an alignment phase-locked loop (PLL), a position of the alignment lines for a respective clock track, determining, using the position of the alignment lines, the position of each respective track, and updating the alignment PLL.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application is a Continuation of U.S. application Ser. No. 12/199,738 filed Aug. 27, 2008, which is a Continuation of U.S. application Ser. No. 11/084,742, filed on, Mar. 21, 2005 now issued U.S. Pat. No. 7,584,402, all of which are herein incorporated by reference.

FIELD OF THE INVENTION

The present invention broadly relates to a method and apparatus for storing digital data on physical surfaces.

Co-Pending Applications

The following applications have been filed by the Applicant with the parent application:

7,540,429 11/084,806

The disclosures of these co-pending applications are incorporated herein by reference.

CROSS-REFERENCES

Various methods, systems and apparatus relating to the present invention are disclosed in the following patents and co-pending applications filed by the applicant or assignee of the present invention. The disclosures of all of these patents and co-pending applications are incorporated herein by cross-reference

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DESCRIPTION OF RELATED ART

DotCards encode data as a series of marks on a card and are described in detail in a series of granted patents and pending patent applications, including U.S. patent application Ser. No. 09/112,781 entitled “Data distribution mechanism in the form of ink dots on cards”.

SUMMARY OF THE INVENTION

In a first form the present invention provides a system for decoding coded data printed in ink on a surface, the coded data having a registration structure, the registration structure having at least two clock tracks indicative of a position of the coded data in the direction perpendicular to an alignment direction and two alignment lines for each clock track, the two alignment lines being indicative of the position of the respective clock track, the system comprising a decoder for:

-   -   determining, using an alignment phase-locked loop (PLL), a         position of the alignment lines for a respective clock track;     -   determining, using the position of the alignment lines, the         position of each respective track; and     -   updating the alignment PLL.         Optionally, the decoder is for decoding the coded data by:     -   determining a transform for each scan line using the alignment         data, the transform being indicative of coordinates of         bit-encoding locations within the data portions; and,     -   detecting bit values using the transform.         Optionally, the decoder is for:     -   determining coordinates of sample values from the coordinates of         the bit-encoding location; and,     -   determining a bit-encoding value by interpolating sample values         from two successive sample lines.         Optionally, the decoder is for:     -   determining the position of at least one marker to determine a         gross registration;     -   determining, using the gross registration, a clock indicator in         a clock track;     -   updating, using the clock indicator, an alignment PLL;     -   determining, using the alignment PLL, a fine registration of the         coded data in the alignment direction.         Optionally, the decoder is for:     -   for each clock track, determining, using a respective data clock         PLL, a position of a clock indicator on the clock track;     -   determining, using the position of the clock indicator on each         clock track, an alignment angle; and     -   updating each data clock PLL.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is an example of an arrangement of Mnem encoding layers;

FIG. 2 is an example of an arrangement of a Mnem area, with m rows of n blocks, in Mnem space;

FIG. 3 is an example of an arrangement of the block structure in block space;

FIG. 4 is an example of a minimum extent of a mark (left) and maximum extent of a mark (right) on a unit block-space grid;

FIG. 5 is an example of a block column state machine;

FIG. 6 is an example of a rotated block in scan space;

FIG. 7 is an example of the rotated block in scan space, showing pilot acquisition points;

FIG. 8 is flowchart of an example of a data decoding process;

FIG. 9 is flowchart of an example of a redundancy decoding process;

FIG. 10 is flowchart of an example of a bitstream parameters decoding process;

FIG. 11 is flowchart of an example of a bitstream decoding process;

FIG. 12 is an example of a rotated block in scan space showing points of intersection between current scanline and data clocks;

FIG. 13 is a block diagram an example of a discrete-time digital PLL

FIG. 14 is a high-level block diagram an example of a Mnem reader;

FIG. 15 is a schematic side view of an example of a media detection, image sensing and transport;

FIG. 16 is a detailed physical view of a Memjet printhead IC with an integral image sensor;

FIG. 17 is a logical view of the printhead and integral image sensor of FIG. 16;

FIG. 18 is a schematic view of an example of an active pixel sensor;

FIG. 19 is a schematic view of an example of a shuttered active pixel sensor;

FIG. 20 is a schematic view of an example of three IC segments abutted to form a wider multi-segment device;

FIG. 21 is a schematic view of an example of the printhead IC packaged and mounted for printing or scanning a medium passing through the same transport mechanism;

FIG. 22 is a schematic exploded perspective view of an example of a MEMJET™ printhead;

FIG. 23 is a schematic cross section of the printhead assembly of FIG. 22 in its assembled form and normal orientation;

FIG. 24 is a schematic plan view of the printhead IC of FIG. 22;

FIG. 25 is a schematic plan view of an example of a linking of printhead ICs;

FIG. 26 is a schematic underside view of an example of the printhead ICs;

FIG. 27 is a schematic perspective view of an example of a printhead nozzle;

FIGS. 28 to 30 show schematic side views of the printhead nozzle of FIG. 27 in use;

FIG. 31 is a schematic side view of a second example of a printhead nozzle;

FIG. 32 is an overview of an example of the integrated circuit and its connections to the print engine controller (PEC);

FIG. 33 is an example of a nozzle column arrangement;

FIG. 34 is an example of a shift register arrangement;

FIG. 35 is an example of connections to a single column;

FIG. 36 is a high-level block diagram of an example of a mnem decoder;

FIG. 37 is a high-level block diagram of an example of a raw decoder;

FIG. 38 is a high-level block diagram of an example of a redundancy decoder;

FIG. 39 is an example of a hole surrounded by eight black marks with no blur;

FIG. 40 is an example histogram of central value for all possible neighbourhoods, for mark (black bar) and hole (gray bars) with no blur;

FIG. 41 is an example of a hole surrounded by eight black marks with a blur radius/mark radius of 9/33;

FIG. 42 is an example histogram of central value for all possible neighbourhoods, for mark (black bar) and hole (gray bars) with a blur radius/mark radius of 9/33;

FIG. 43 is an example of a hole surrounded by eight black marks with a blur radius/mark radius of 12/33; and,

FIG. 44 is an example histogram of central value for all possible neighbourhoods, for mark (black bar) and hole (gray bars) with a blur radius/mark radius of 12/33.

DETAILED DESCRIPTION OF PREFERRED EXAMPLES 1. Introduction

Mnem is a robust two-dimensional optical encoding scheme for storing digital data on physical surfaces. Its data capacity scales linearly with surface area. It fundamentally supports read-only (RO) and write-once read-many (WORM) applications, and includes the ability to append data. It incorporates optional fault tolerance to cope with real-world surface degradation.

Mnem is suitable for inkjet printing. When printed using an invisible ink such as an infrared absorptive or fluorescent ink, Mnem-encoded data may be superimposed on visible text and colour graphics. This allows, for example, a digital negative of a photograph to be superimposed on a colour print of the photograph.

Mnem is optimised for efficient real-time decoding during a linear scan of Mnem-encoded data. A compact Mnem decoder chip implements the decoding function. In an application where data is encoded on card media, the decoder chip is typically coupled with a linear image sensor and a card transport mechanism. The decoder then functions in real time as the card is transported past the linear image sensor.

The Mnem decoder operates entirely without software intervention, and writes decoded data contiguously to external memory. It provides both raw and fault-tolerant operating modes, and in fault-tolerant mode requires only a small amount of additional external memory for temporary storage of parameter and redundancy data. The decoder optionally controls image acquisition and media transport.

This document describes the Mnem format, the decoding algorithm, and the architecture of a decoder and a complete reader.

The Mnem design builds on the earlier dotCard design, which is described in detail in a series of granted patents and pending patent applications, including U.S. patent application Ser. No. 09/112,781 entitled “Data distribution mechanism in the form of ink dots on cards”, all other patents and pending applications on this technology are provided in the cross-references section above. It differs from dotCard in being optimised for efficient decoding. Differences between the two approaches are described in detail below.

2. Format

A Mnem area encodes one or more bitstreams of data. These are numbered sequentially from zero. The bits within a bitstream are also numbered sequentially from zero.

As illustrated in FIG. 1, the Mnem encoding has a physical layer, a raw data layer, and a fault-tolerant data layer. The raw data layer represents each bitstream using a two-dimensional encoding scheme. The physical layer implements the encoding scheme in a form suitable for optical sensing and imaging. The fault-tolerant data layer encodes each bitstream redundantly for fault tolerance.

The physical layer can vary according to application. A Mnem application can choose to use Mnem's fault-tolerant data layer or implement its own.

2.1 Raw Data Layer 2.1.1 Bitstream Segmentation

Each bitstream is partitioned into a sequence of segments. Within a bitstream, these are numbered sequentially from zero. The segment size is fixed for a particular application.

Each segment is represented by a two-dimensional block, and a bitstream is therefore represented by a sequence of blocks. Each block includes sufficient structure to allow it to be detected, and its segment data decoded, independently of other blocks. The block structure of a Mnem area serves two purposes: (a) it allows required optical tolerances to be met locally per block rather than globally for the entire Mnem area; and (b) it provides the basis for appending a new bitstream to an existing Mnem area.

The structure of a Mnem area is defined within a Cartesian coordinate space referred to as Mnem space, as illustrated in FIG. 2. Each block has a corresponding location within the area. Increasing block numbers correspond to block locations with increasing x coordinates within increasing y coordinates, thus defining a set of block rows. The first block of a stream follows the last block of the previous stream, if any.

There is a nominal edge-to-edge spacing Δ_(b) between blocks, and each block has a nominal position based on the nominal spacing. The actual position of a block is allowed to vary by up to ±Δ_(b)/2 in either or both dimensions. The spacing is application specific.

There is a nominal minimum spacing Δ_(m) in the x dimension between the edge of the Mnem area and the edge of the scan. The actual position of the Mnem area with respect to the scan is allowed to vary in x by ±Δ_(m). The spacing is application specific.

Assuming a maximum allowed block height of H_(b max), a maximum allowed block width of W_(b max), Mnem area height of H_(m), and a Mnem area width of W_(m), the number m of block rows and the number n of block columns in the Mnem area are given by:

$\begin{matrix} {m = \left\lfloor \frac{H_{m}}{H_{b_{\max}} + \Delta_{b}} \right\rfloor} & \left( {{EQ}\; 1} \right) \\ {n = \left\lfloor \frac{W_{m}}{W_{b_{\max}} + \Delta_{b}} \right\rfloor} & \left( {{EQ}\; 2} \right) \end{matrix}$

The nominal height H_(b)′ and actual width W_(b) of a block are then given by:

$\begin{matrix} {H_{b}^{\prime} = {\left\lfloor \frac{H_{m}}{m} \right\rfloor - \Delta_{b}}} & \left( {{EQ}\mspace{14mu} 3} \right) \\ {W_{b} = {\left\lfloor \frac{W_{m}}{n} \right\rfloor - \Delta_{b}}} & \left( {{EQ}\mspace{14mu} 4} \right) \end{matrix}$

The actual height H_(b) of a block is derived in Section 2.1.6.

The structure of the block is defined within a Cartesian coordinate space referred to as block space, as illustrated in FIG. 3. Note that the various block components shown in the figure are not to scale.

Block space and Mnem space have the same scale and rotation. They are related by a translation. The block in column i and row j has a block space to Mnem space translation vector T_(bm):

T _(bm)(i,j)=[Δ_(b) +i(W _(b)+Δ_(b)),Δ_(b) +j(H _(b)+Δ_(b)),0]^(T)  (EQ 5)

2.1.2 Data Grid

Within the block each data bit of the segment has a corresponding encoding location, and the value of the bit is encoded by the presence or absence of a mark at that location. The presence of a mark encodes a one bit; the absence of a mark encodes a zero bit. The bit encoding locations are arranged on a regular rectangular grid. Each location has integer coordinates and the spacing of adjacent locations is one unit in both x and y. Increasing bit numbers correspond to locations with increasing y coordinates within increasing x coordinates, thus defining a row of data columns.

The width W_(d) and height H_(d) of the data grid are derived from the block dimensions in Section 2.1.6. The height of the data grid is always a multiple of 8.

2.1.3 Pilot

The block is designed to be scanned in the y direction, i.e. using a set of scanlines more or less parallel to the x axis. It therefore includes a pilot sequence at the bottom to allow initial block detection. The structure of the block is rotationally symmetric to allow it to be scanned bottom-to-top or top-to-bottom. It includes a different pilot sequence at the top to allow the decoder to detect the scan direction and correct for it. Support for bi-directional scanning may be omitted for applications which don't require it.

The block is designed to allow scanning and decoding even when slightly rotated with respect to the scan direction, up to a maximum rotation α_(max), to accommodate real-world tolerances in a reader as well as in the encoding itself (e.g. due to the original printing process). The pilot therefore allows the decoder to determine the actual rotation α of the block with respect to the scan direction.

The pilot consists of a binary sequence encoded at odd y coordinates, i.e. using a return-to-zero representation. This allows it to be self-clocking. The presence of a line parallel to the x axis encodes a one bit; the absence of a line encodes a zero bit.

The pilot sequence consists of a lead-in which assists initial synchronisation, followed by a unique code sequence which allows recognition and registration. The lead-in consists of five consecutive ones. The bottom pilot code sequence is 110101100100011; the top pilot code sequence is 110010001111010, i.e. a left cyclic 5-shift of the bottom pilot code sequence. The height H_(p) of the pilot is 40 units. The width W_(p) of the pilot is defined relative to the width of the data grid and the width of the data clock tracks (see Section 2.1.5).

The two pilot code sequences are selected to maximise their binary Hamming distance. This allows the decoder to perform maximum-likelihood detection of the pilots even in the presence of errors. The pilots are also selected to maximise their Hamming distance from sequences which result from an arbitrary prefix of one bits, e.g. such as when preceded by the lead-in.

Once the decoder detects the pilot sequence it knows the y registration of the block with respect to the scan. By detecting the pilot sequence at two different x offsets it obtains two potentially different y registrations for the block. From these it can compute the slope of the pilot lines and hence the initial slope of the data grid. By attempting to detect the pilot at more than two locations the decoder can more robustly detect the pilot.

2.1.4 Registration Tracks

The block contains a registration track following each pilot. Each registration track consists of a clock track interspersed with registration markers at regular intervals. The markers allow the decoder to determine the gross x registration of the block, i.e. to within a clock period (or equivalently ±1 unit). The clock track allows the decoder to determine the fine x registration of the block, i.e. to within a fraction of a clock period.

The clock track consists of a sequence of clock ticks positioned on successive odd x coordinates. Each clock tick consists of a short line, parallel to the y axis.

The registration markers have a width W_(f) and an edge-to-edge spacing Δ_(f) sufficiently large to allow the decoder to unambiguously locate and identify each marker even if the deviation in the x position of the block from its nominal x position is the maximum allowed:

W _(f)=Δ_(m)+Δ_(b) +W _(f min)  (EQ 6)

Δ_(f)=Δ_(m)+Δ_(b)+Δ_(f min)  (EQ 7)

W_(f min) is the minimum marker size. It has a fixed value defined in Table 2. Δ_(f min) is the minimum marker separation. It has a fixed value defined in Table 2.

The left-most marker associated with the bottom pilot is aligned with the first column of the registration track, and the remaining markers are positioned relative to the left-most marker. The right-most marker associated with the top pilot is aligned with the last column of the registration track, and the remaining markers are positioned relative to the right-most marker. The width W_(r) of the marker track is defined relative to the width of the data grid and the width of the data clock tracks (see Section 2.1.5).

The registration markers and clock ticks have a height H_(r) sufficient to guarantee that the decoder encounters the entire registration track before encountering the start of the data grid, even if the rotation of the block with respect to the scan direction is the maximum allowed:

H _(r)=2(└(┌W _(r) tan α_(max) ┐+H _(r min)−1)/2┘+1)  (EQ 8)

The height is even to correspond to an integer number of data clocks. H_(r min) is the minimum distance required to allow an individual marker to be detected. It has a fixed value defined in Table 2.

There are a redundant number of markers. At a minimum the decoder need only detect one marker and process its adjacent clock.

2.1.5 Data Clock Tracks

The block contains two clock tracks running along the two vertical sides of the data grid, for the full height of the block. Each clock track consists of a sequence of clock ticks positioned on successive odd y coordinates. Each clock tick consists of a short line, parallel to the x axis. Each clock track also contains two alignment lines parallel to the y axis, running the full height of the clock track. The alignment lines are separated from each other and from the clock ticks by a blank line. With respect to the data grid, the alignment lines run along the outside edge of each clock track.

Once the decoder knows the y and x registration of the block and the initial slope of the data grid via the pilot and registration track, it is able to track the two clocks from one scanline to the next. It thus obtains two potentially different y registrations for the two ends of each scanline, and from these it can compute the slope of the scanline and sample each bit-encoding location the scanline intersects. The decoder can use the slope of the scanline to update its estimate of the slope of the clock tracks, to help it track the centre of each clock track.

The decoder tracks the centre of each clock track by tracking the centre of the blank line between the two alignment lines.

The width W_(c) of each clock track is the width of a clock tick, alignment lines and spacing:

W _(c) =W _(ct)+4  (EQ 9)

The width W_(ct) of a clock tick has a fixed value defined in Table 2.

Where the clock tracks run alongside registration track they have a greater width W_(w) to allow the decoder to acquire and track the clocks before it acquires x registration via the registration track:

W _(w) =┌W _(c)(1+sin α_(max))┐+Δ_(m)+Δ_(b)  (EQ 10)

2.1.6 Block Component Spacing

There is a blank border around the entire block one unit wide. This ensures separation of adjacent blocks' pilots and alignment lines even when Δ_(b)=0.

Each pilot is separated from its corresponding registration track by a blank line.

There is a blank border around the entire data grid one unit wide. This simplifies assumptions during decoding about the values of bit-encoding locations in the neighbourhood of any given bit-encoding location.

Because the height of the data grid is even but the height of the data clock tracks is odd, the border between the top registration track and the data grid is two units high.

The non-data height overhead H_(h) and width overhead W_(h) are given by:

H _(h)=2(H _(p) +H _(r)+3)+1  (EQ 11)

W _(h)=2(W _(c)+2)  (EQ 12)

The overall height H_(d) and width W_(d) of the data grid are given by:

$\begin{matrix} {H_{d} = {8\left\lfloor \frac{H_{b}^{\prime} - H_{h}}{8} \right\rfloor}} & \left( {{EQ}\mspace{14mu} 13} \right) \\ {W_{d} = {W_{b} - W_{h}}} & \left( {{EQ}\mspace{14mu} 14} \right) \end{matrix}$

The raw byte capacity D_(m) of a Mnem area is given by:

$\begin{matrix} {D_{m} = \frac{{mnH}_{d}W_{d}}{8}} & \left( {{EQ}\mspace{14mu} 15} \right) \end{matrix}$

Given the data grid height H_(d), the actual height H_(b) of the block is given by:

H _(b) =H _(h) +H _(d)  (EQ 16)

The position P_(f0) of the bottom right corner of the first gross registration marker is given by:

P _(f0)=(x _(f0) ,y _(f0),1)^(T)=(W _(w)+2+W _(f) ,H _(p)+2,1)^(T)  (EQ 17)

The position P_(f) of the bottom right corner of gross registration marker j is given by:

P _(f)(i)=(x _(f)(i),y_(f0),1)^(T) =P _(f0) +[i(Δ_(f) +W _(f)),0,0]^(T)  (EQ 18)

The position P_(d0) of the first (i.e. bottom left) bit-encoding location in the data grid is given by:

P _(d0)=(x _(d0) ,y _(d0),1)^(T)=(W _(c)+2,H _(p) +H _(r)+3,1)^(T)  (EQ 19)

The position P_(d) of the bit-encoding location in column i and row j of the data grid is given by:

P _(d)(i,j)=P _(d0) +[i,j,0]^(T)  (EQ 20)

For completeness, the width of the pilots and the registration tracks are given by:

W _(p) =W _(b)−2  (EQ 21)

W _(r) =W _(b)−2(W _(w)+2)  (EQ 22)

2.2 Physical Layer

A mark has a position with integer coordinates. As illustrated in FIG. 4, it has a minimum extent equal to the area of a unit square centred at its position, and a maximum extent equal to the area of the circle circumscribing this unit square.

A line is parallel to the x axis or to the y axis, and its endpoints have integer coordinates. It traverses a set of points with integer coordinates. Its extent is identical to that of a set of marks placed at these points.

A mark, when illuminated and imaged optically, has a response which contrasts with that of the unmarked surface. Although the spectral characteristics of the unmarked surface, the mark, and the imaging system are application specific, the surface is typically broadband reflective while the mark is typically broadband or narrowband absorptive.

Example representations include a black mark on a white surface, and an near-infrared-absorptive mark on a white surface.

For clarity in the remainder of this document, marks are referred to and shown as black, while unmarked surface areas are referred to and shown as white. The absence of a mark is also referred to as a hole.

The real space to Mnem space scale factor R determines the real spatial density of the Mnem area.

When printed using a 1600 dpi Memjet printing system, the design of which has been disclosed in a series of Granted patents and pending patent applications listed in the cross references above, and which is described in more detail in Section 9, with each mark corresponding to a single Memjet dot, R is 1600 per inch or 63 per mm, and the extent of each mark is at its allowed maximum.

2.3 Fault-Tolerant Data Layer

As described above, the block structure of the raw data layer is inherently fault tolerant. The fault-tolerant data layer adds data fault-tolerance.

Mnem uses Reed-Solomon redundancy coding and interleaving to provide data fault tolerance. Each bitstream is interpreted as a stream of 8-bit symbols for the purposes of encoding. During encoding the symbol stream is interleaved according to an interleave factor, Reed-Solomon encoded, and then de-interleaved. This leaves the bitstream in its original state, but ensures maximum separation between symbols belonging to the same Reed-Solomon codeword. The interleave factor is chosen to match the number of Reed-Solomon codewords required to encode the entire bitstream. This ensures that after de-interleaving all redundancy data appears appended to the end of the original bitstream. The original bitstream is zero-padded to make its size an integer multiple of the code's dimension (i.e. the codeword's data capacity).

An application can choose to replicate a short bitstream any number of times to increase fault tolerance. Both the replication and the increased interleaving increase fault tolerance.

Mnem uses the 8-bit (255,233) CCSDS code (CCSDS, Recommendations for Telemetry Channel Coding, CCSDS 101.0-B-6, October 2002), which has an error-correcting capacity of 16 symbols per codeword.

To allow the decoder to decode an encoded bitstream, it must know the interleave factor of the bitstream and the number of codewords in the bitstream. In Mnem these are the same. The fault-tolerant layer encodes the number and the size of the encoded bitstream alongside the bitstream itself. Since these parameters cannot benefit from the fault tolerance of the encoded bitstream, the bitstream parameters are replicated multiple times in each block. A cyclic redundancy check (CRC) sequence is appended to each copy to allow the decoder to detect a good copy. Alternatively or additionally, the bitstream parameters can be Reed-Solomon encoded independently of the bitstream, using a shorter Reed-Solomon code with more redundancy.

The first and last columns of the data grid of each block are set aside for encoding the bitstream parameters and their CRC. These are repeated as many times as will fit in the height of the data column. The bitstream number is encoded as a 16-bit integer. The bitstream size is encoded as a 32-bit unsigned integer. The CRC is the 16-bit CRC defined by the CCITT (ITU, Interface between Data Terminal Equipment (DTE) and Data Circuit-terminating Equipment (DCE) for terminals operating in the packet mode and connected to public data networks by dedicated circuit, ITU-T X.25 (10/96)). Both the parameters and the CRC are encoded most-significant byte and bit first, i.e. with the lowest bit number and y coordinate.

The encoded byte capacity E_(m) of a Mnem area is given by:

$\begin{matrix} {E_{m} = {223\left\lfloor \frac{{mnH}_{d}\left( {W_{d} - 2} \right)}{255 \times 8} \right\rfloor}} & \left( {{EQ}\mspace{14mu} 23} \right) \end{matrix}$

2.4 Summary of Parameters

Table 1, Table 2 and Table 3 summarise the variable, fixed and derived parameters which define the Mnem format.

TABLE 1 Variable parameters parameter description α_(max) Maximum α, the rotation of the block in scan space. Δ_(b) The nominal edge-to-edge spacing between adjacent blocks, and twice the maximum block misalignment. Δ_(m) The nominal minimum x spacing between the edge of the Mnem area and the edge of the scan, and the maximum horizontal Mnem area misalignment. H_(b max) The maximum height of a block. H_(m) The height of the Mnem area. N The sampling rate, i.e. the nominal block space to scan space scale factor. R The real space to Mnem space scale factor. W_(b max) The maximum width of a block. W_(m) The width of the Mnem area. {tilde over (W)}_(s) The width of the scanline.

TABLE 2 Fixed Parameters parameter value description Δ_(f min) 20 Minimum Δ_(f), the edge-to-edge spacing between adjacent registration markers. H_(p) 40 The height of the pilot. H_(r min) 3 Minimum H_(r), the height of the registration track. W_(ct) 3 The width of a data clock tick. W_(f min) 20 Minimum W_(f), the width of a registration marker.

TABLE 3 Derived parameters parameter equation description Δ_(f) EQ 7 The edge-to-edge spacing between adjacent registration markers. D_(m) EQ 15 The raw bit capacity of the Mnem area. E_(m) EQ 23 The encoded bit capacity of the Mnem area. H_(b) EQ 16 The height of the block. H_(b)′ EQ 3 The nominal height of the block. H_(d) EQ 13 The height of the data grid (always a multiple of 8). H_(h) EQ 11 The height of the block overhead. H_(r) EQ 8 The height of the registration track. m EQ 1 The number of block rows in the Mnem area. n EQ 2 The number of block columns in the Mnem area. T_(bm) EQ 5 The block space to Mnem space translation vector. W_(b) EQ 4 The width of the block. W_(c) EQ 9 The width of the data clock track. W_(d) EQ 14 The width of the data grid. W_(f) EQ 6 The width of a registration marker. W_(h) EQ 12 The width of the block overhead. W_(p) EQ 21 The width of the pilot. W_(r) EQ 22 The width of the registration track. W_(w) EQ 10 The width of the wide data clock track.

3. Decoding Algorithm 3.1 Raw Data Layer Decoding

A Mnem block is designed to be scanned in the y direction, i.e. using a set of scanlines more or less parallel to the x axis. Furthermore, it is designed to be incrementally decodable using only the two most recent scanlines. The decoder is therefore only required to buffer the last two scanlines (or three, depending on image sensor performance), and this in turn makes it practical to buffer scanlines in on-chip memory rather than in off-chip memory.

Scanline decoding makes it practical to decode a Mnem area in real time during scanning. In a typical configuration, a Mnem area is encoded on the surface of a laminar medium such as a paper or plastic sheet, and the decoder operates while the encoded sheet is transported past a linear image sensor.

Although the decoder only requires incremental scanline access to a Mnem area, this does not preclude area scanning of a Mnem area.

As illustrated in FIG. 2, a Mnem area encodes m block rows of n blocks each. For the purposes of scan decoding, this can be thought of as n block columns of m blocks each. Note that trailing blocks in the last row need not be present. Furthermore, when scan processing is proceeding top-to-bottom rather than bottom-to-top, this can manifest itself as the absence of leading blocks in the first row.

During the processing of a single scanline, the decoder operates on each of the n block columns in the Mnem area. It maintains a state for each column, reflecting the state of the decoding algorithm for that column. The block columns need not be in the same state during the processing of a single scanline. The block column state machine is shown in FIG. 5 and is described below.

The scan proceeds within a Cartesian coordinate space referred to as scan space, as illustrated in FIG. 6. An x unit in scan space corresponds to the spatial sampling period d_(x) of the scanline, i.e. the horizontal pixel pitch of the scanline. A y unit in scan space corresponds to the spatial sampling period d_(y) of the scan, i.e. the vertical pitch of the scan. These units are nominally equal. As described earlier, the block is rotated by a with respect to scan space, up to a maximum α_(max). The block is also arbitrarily translated with respect to scan space. Scan space and block space are therefore related by an arbitrary affine transform.

Throughout this document, scan-space quantities are indicated by a tilde.

Given a scan sampling rate N with respect to block space, the width {tilde over (W)}_(s) of scan space is sufficient to image the Mnem area throughout the scan:

{tilde over (W)}_(s) ≧N(W _(m)+2Δ_(m))+2NH _(m) sin α_(max)  (EQ 24)

The reader informs the decoder of the nominal scan-space position Õ_(m) of the origin of Mnem space. In some applications this will be a fixed parameter, e.g. where the Mnem area has a fixed location relative to the edges of a card medium. In other applications the reader may utilise additional information, such as additional target structures encoded on the medium, to determine the origin dynamically.

The decoder uses the scan-space position Õ_(m) of the origin of Mnem space to compute the nominal scan-space position Õ_(b) of the origin of block space for the first block in each block column i:

{tilde over (O)}_(b)(i)=({tilde over (x)}_(ob)(i),{tilde over (y)}_(ob),1)^(T=) Õ _(m) +NT _(bm)(i,0)  EQ 25)

where T_(bm) is the block space to Mnem space translation vector defined in EQ 5.

3.1.1 Detect Pilot

When the block decoder is in the <detect pilot> state, it attempts to detect the pilot at two (or more) different x locations in the scan. At each location it uses a PLL to lock onto the clock inherent in the pilot, and samples and accumulates pilot bit values according to the clock as the scan progresses. It uses the fractional y coordinate of the clock peak to linearly interpolate the bit value.

In general, assuming two adjacent scan-space samples yield clock phases θ_(a) and θ_(b) respectively, detecting a clock peak in scan space involves detecting a transition across a 2π boundary:

$\begin{matrix} {\left\lfloor \frac{\theta_{a}}{2\pi} \right\rfloor < \left\lfloor \frac{\theta_{b}}{2\pi} \right\rfloor} & \left( {{EQ}\mspace{14mu} 26} \right) \end{matrix}$

Once a peak is detected, its fractional scan-space displacement {tilde over (g)} (in the x or y dimension as appropriate) is defined as follow:

$\begin{matrix} {{\overset{\sim}{g} = \frac{{2\pi} - {{mod}\left( {\theta_{a},{2\pi}} \right)}}{{2\pi} - {{mod}\left( {\theta_{a},{2\pi}} \right)} + {{mod}\left( {\theta_{b},{2\pi}} \right)}}}{{where}\text{:}}} & \left( {{EQ}\mspace{14mu} 27} \right) \\ {{{mod}\left( {\theta,p} \right)} = {\theta - \left\lfloor \frac{\theta}{p} \right\rfloor}} & \left( {{EQ}\mspace{14mu} 28} \right) \end{matrix}$

The decoder uses a maximum-likelihood decoder to decode the accumulated pilot sequence and detect pilot acquisition. When it acquires the pilot at two locations it computes the initial y registration and rotation a of the block in scan space. The decoder then enters the <await registration track> state.

Assuming two scan-space pilot acquisition points of ({tilde over (x)}_(a), {tilde over (y)}_(a), 1)^(T) and ({tilde over (x)}_(b), {tilde over (y)}_(b), 1)^(T), the block rotation α is given by:

$\begin{matrix} {{\tan \; \alpha} = \frac{{\overset{\sim}{y}}_{b} - {\overset{\sim}{y}}_{a}}{{\overset{\sim}{x}}_{b} - {\overset{\sim}{x}}_{a}}} & \left( {{EQ}\mspace{14mu} 29} \right) \\ {\alpha = {{atan}\left( \frac{{\overset{\sim}{y}}_{b} - {\overset{\sim}{y}}_{a}}{{\overset{\sim}{x}}_{b} - {\overset{\sim}{x}}_{a}} \right)}} & \left( {{EQ}\mspace{14mu} 30} \right) \end{matrix}$

The two acquisition points have the same clock phase θ_(p), defined to be 2πH_(p) based on the first lead-in line having a phase of 2π.

In general, it is useful to know the clock phase difference δ which corresponds to one scan-space unit. Given phases θ_(u) and θ_(v) measured at recent scan-space locations ({tilde over (x)}, {tilde over (y)}_(u), 1)^(T) and ({tilde over (x)}, {tilde over (y)}_(v), 1)^(T), δ is given by:

$\begin{matrix} {\delta = \frac{\theta_{u} - \theta_{v}}{{\overset{\sim}{y}}_{u} - {\overset{\sim}{y}}_{v}}} & \left( {{EQ}\mspace{14mu} 31} \right) \end{matrix}$

Since the frequency of all Mnem clocks is the same, δ can be computed from any recently-measured data clock phases, in either the x or y dimension.

δ is inversely proportional to the scale and rotation term X in the block space to scan space transform developed in Section 5:

$\begin{matrix} {X = {{S\; \cos \; \alpha} = \frac{2\pi}{\delta}}} & \left( {{EQ}\mspace{14mu} 32} \right) \end{matrix}$

After pilot acquisition, the decoder computes the correct initial phase for each wide data clock, i.e. corresponding to the scanline immediately after pilot acquisition.

Given the pilot processing point {tilde over (P)}_(q)=({tilde over (x)}_(q), {tilde over (y)}_(q), 1)^(T) on the next scanline after pilot acquisition, as shown in FIG. 7, the decoder computes the scan-space x coordinates {tilde over (x)}_(wl) and {tilde over (x)}_(wr) of the nominal centres of the left and right wide data clocks from the scan-space position Õ_(b) of the origin of block space, the block space to scan space scale and rotation term X, and the block rotation α:

$\begin{matrix} {{\overset{\sim}{x}}_{wl} = {{\overset{\sim}{x}}_{ob} + {X\; \frac{W_{w}}{2}} + {\left( {{\overset{\sim}{y}}_{q} - {\overset{\sim}{y}}_{ob}} \right)\tan \; \alpha}}} & \left( {{EQ}\mspace{14mu} 33} \right) \\ {{\overset{\sim}{x}}_{wr} = {{\overset{\sim}{O}}_{b} + {X\left( {W_{b} - \frac{W_{w}}{2}} \right)} + {\left( {{\overset{\sim}{y}}_{q} - {\overset{\sim}{y}}_{ob}} \right)\tan \; \alpha}}} & \left( {{EQ}\mspace{14mu} 34} \right) \end{matrix}$

In the figure, solid lines indicate integer coordinates and dashed lines indicate fractional coordinates.

Assuming the pilot processing point {tilde over (P)}_(q) has a clock phase θ_(q), the decoder first adjusts its clock phase relative to the known phase of the pilot before using it:

θ_(q)′=θ_(p)+mod(θ_(q),2π)  (EQ 35)

Given the desired nominal scan-space x coordinate {tilde over (x)}_(w) of the centre of a wide data clock, the decoder computes the correct phase θ_(w) for the clock:

θ_(w)=θ_(q)′−({tilde over (x)}_(q) −{tilde over (x)} _(w))δ tan α  (EQ 35)

Note that if the decoder chooses to acquire the pilot at x locations which lie within the bounds of the wide data clocks, then it can continue to track the data clocks at the same x locations, with only the phase adjustment indicated by EQ 35.

The decoder continuously tracks the two data clocks throughout the subsequent decoding stages. This includes computing the intersection point of each scanline with the centre of each data clock track, as described in Section 4. The decoder uses these intersection points to compute the block space to scan space transform, as described in Section 5, and to identify which scanline pixels to use to update the data clocks.

3.1.2 Await and Detect Registration Track

In the <await registration track> state the decoder skips scanlines until the current scanline lies within the registration track. It then enters the <detect registration track> state.

In the <detect registration track> state the decoder searches for one or more registration markers within the registration track. Once it detects a good marker it computes the initial gross x registration of the block in scan space. It then uses a PLL to lock onto the clock adjacent to the marker, to determine the fine x registration of the block. The decoder may repeat this process multiple times with different markers to achieve redundancy, e.g. three times with a majority vote on the result.

The nominal scan-space position {tilde over (P)}_(f) of each gross registration marker i is given by:

{tilde over (P)}_(f)(i)={tilde over (O)}_(b) +NP _(f)(i)(1+sin α)  (EQ 37)

This is based on the actual block-space position P_(f) and the nominal scan-space position Õ_(b) of the block origin.

When the decoder detects the right edge of a marker at a scan-space x coordinate {tilde over (x)}_(f), it computes the corresponding marker index by solving for integer i in EQ 37:

$\begin{matrix} {i = \left\lfloor {\frac{{\overset{\sim}{x}}_{f} - {\overset{\sim}{x}}_{ob}}{{N\left( {\Delta_{f} + W_{f}} \right)}\left( {1 + {\sin \; \alpha}} \right)} + 0.5} \right\rfloor} & \left( {{EQ}\mspace{14mu} 38} \right) \end{matrix}$

The decoder uses the marker index i to compute the correct block-space x coordinate x_(f) of the marker using EQ 17.

Since the decoder detects the edge of a marker at a y coordinate y_(f)′ which is typically larger than the starting y coordinate y_(f) of the marker (as given by EQ 17), the decoder adjusts the detected x coordinate x_(f) according to the block rotation α and y offset:

x _(f) ′=x _(f)+(y _(f) ′−y _(f))tan α  (EQ 39)

Since there is some uncertainty in the decoder's estimate of the scan-space x coordinate {tilde over (x)}_(f) of the right edge of the marker, the decoder uses the clock adjacent to the marker to refine the estimate.

The decoder uses a PLL to lock onto and track the x registration clock. It initialises the phase of the PLL to zero, and then iterates the PLL using successive scanline pixels. Assuming the phase of the clock is θ_(r) at a scan-space x coordinate {tilde over (x)}_(r) some distance along the scanline from the x coordinate {tilde over (x)}_(f) at which the decoder detected the right edge of the marker, the decoder refines the block-space x coordinate x_(f) using a correction factor based on the difference between the expected and actual phase at {tilde over (x)}_(r):

$\begin{matrix} {x_{f}^{\prime} = {x_{f} + \frac{{{mod}\left( {{\delta \left( {{\overset{\sim}{x}}_{r} - {\overset{\sim}{x}}_{f}} \right)},\pi} \right)} - {{mod}\left( {\theta_{r},\pi} \right)}}{\pi}}} & \left( {{EQ}\mspace{14mu} 40} \right) \end{matrix}$

After determining x registration via the registration track, the decoder computes the correct initial phase for each narrow data clock PLL and its associated alignment PLL, i.e. corresponding to the last scanline used to acquire registration.

Given the registration processing point {tilde over (P)}_(s)=({tilde over (x)}_(s), {tilde over (y)}_(s), 1)^(T), the decoder computes the scan-space x coordinates {tilde over (x)}_(cl) and {tilde over (x)}_(cr) of the centres of the left and right data clocks from the scan-space position Õ_(b) of the origin of block space, the block space to scan space scale and rotation term X, and the block rotation α:

$\begin{matrix} {{\overset{\sim}{x}}_{cl} = {{\overset{\sim}{x}}_{ob} + {X\; \frac{W_{c}}{2}} + {\left( {{\overset{\sim}{y}}_{s} - {\overset{\sim}{y}}_{ob}} \right)\tan \; \alpha}}} & \left( {{EQ}\mspace{14mu} 41} \right) \\ {{\overset{\sim}{x}}_{cr} = {{\overset{\sim}{x}}_{ob} + {X\left( {W_{b} - \frac{W_{c}}{2}} \right)} + {\left( {{\overset{\sim}{y}}_{s} - {\overset{\sim}{y}}_{ob}} \right)\tan \; \alpha}}} & \left( {{EQ}\mspace{14mu} 42} \right) \end{matrix}$

Assuming the registration processing point {tilde over (P)}_(s) has a vertical clock phase θ_(s), and given the desired scan-space x coordinate {tilde over (x)}_(c) of the centre of a data clock, the decoder computes the correct phase θ_(c) for the clock:

θ_(c)=θ_(s)−({tilde over (x)}_(s) −{tilde over (x)} _(w))δ tan α  (EQ 43)

Although phase values are computed in radians throughout this specification, in the decoder implementation it may be convenient to compute phase values in cycle or half-cycle units, and convert to radians explicitly or implicitly as required. Half-cycle units are attractive because they unify block space units and phase units.

3.1.3 Await and Decode Data

In the <await data> state the decoder skips scanlines until the current scanline intersects the data area. It then enters the <decode data> state.

In the <decode data> state the decoder attempts to decode bit data from each successive scan line.

Although two bits in adjacent data columns may have adjacent bit-encoding locations in block space, the decoder may decode these bits from different scanlines since scanlines are not in general parallel to the x axis in block space. The decoder therefore maintains a current bit index j for each data column, which identifies the encoding location of the next bit to be decoded for that column.

To decode bit data from the current scanline, the decoder visits each data column in turn and computes the fractional scan-space (“pixel”) coordinates {tilde over (P)}_(d)=({tilde over (x)}_(d),{tilde over (y)}_(d), 1)^(T) of its pending bit-encoding location. To compute the coordinates of the first column's bit-encoding location, the decoder uses the block space to scan space transform M just computed from the two data clocks, as described in Section 5:

{tilde over (P)}_(d)(0,j)=M·P _(d0) +j{tilde over (d)} _(y)  (EQ 44)

To compute the coordinates of a subsequent column's bit-encoding locations, the decoder adds the column increment vector {tilde over (d)}_(x) the coordinates of the previous column's bit-encoding location:

{tilde over (P)}_(d)(i,j)={tilde over (P)}_(d)(i−1,j)+{tilde over (d)}_(x)  (EQ 45)

If the bit index changes from one column to the next, then the decoder also adds (or subtracts) the row increment vector {tilde over (d)}_(y):

{tilde over (P)}_(d)(i,j)={tilde over (P)}_(d)(i−1,j±1)+{tilde over (d)}_(x) ±{tilde over (d)} _(y)  (EQ 46)

If the integer portion of the pixel y coordinate of the bit-encoding location matches the y coordinate {tilde over (y)}_(s) of the current scanline, i.e.:

{tilde over (y)}_(s)=└{tilde over (y)}_(d)┘  (EQ 47)

then the decoder computes the grayscale value v of the corresponding bit by bi-linearly interpolating the values of the corresponding four pixels from the current and next scanline, i.e. the four pixel values v₀₀, v₀₁, v₁₀, and v₁₁ at:

{tilde over (P)}₀₀=(└{tilde over (x)}_(d)┘,{tilde over (y)}_(s),1)^(T) , {tilde over (P)} ₀₁=(└{tilde over (x)}_(d)┘+1,{tilde over (y)} _(s),1)^(T) , {tilde over (P)} ₁₀=(└{tilde over (x)}_(d) ┘,{tilde over (y)} _(s)+1,1)^(T), and {tilde over (P)}₁₁=(└{tilde over (x)}_(d)┘+1,{tilde over (y)} _(s)+1,1)^(T):

v ₀ =v ₀₀ +f _(x)(v ₀₁ −v ₀₀)  (EQ 48)

v ₁ =v ₁₀ +f _(x)(v ₁₁ −v ₁₀)  (EQ 49)

v=v ₀ +f _(y)(v ₁ −v ₀)  (EQ 50)

The interpolation factors f_(x) and f_(y) are the fractional parts of the encoding location's pixel coordinates:

f _(x) ={tilde over (x)} _(d) −└{tilde over (x)} _(d)┘  (EQ 51)

f _(y) ={tilde over (y)} _(d) −└{tilde over (y)} _(d)┘  (EQ 52)

The decoder computes the coordinates of the first column's bit-encoding location using the transform from block space to scan space. It computes the coordinates of subsequent columns' bit-encoding locations by adding an x delta for every column and a y delta for every column which has a different block-space y coordinate to its predecessor. Because the maximum block rotation is constrained, the maximum block-space y delta between adjacent columns is plus or minus one.

Correct thresholding of the grayscale value v to obtain the bit value is aided by knowledge of the values of neighbouring bits, since bit-encoding marks are allowed to overlap. Since subsequent bit values in the scan direction are not yet available, an un-resolved multi-level value is temporarily recorded. This is resolved into a bit value once the subsequent bit values are known.

FIG. 8 shows a flowchart of the data decoding process.

Section 12 shows the distribution of imaged grayscale values for a central bit-encoding location for all possible arrangements of its eight neighbouring marks. As image blur increases, the separation between the range of possible values representing a mark and the range of possible values representing a hole decreases to zero.

Potential sources of image blur include motion blur, defocus blur, and intrinsic imaging blur. Motion blur typically occurs in the scan direction if the encoded medium is scanned while in continuous motion.

A Mnem reader typically incorporates a well-controlled imaging environment. This allows a nominal threshold separating the mark and hole ranges to be calibrated. If blur is well-controlled, then this single threshold allows accurate decoding. To deal with blur-induced ambiguity in the vicinity of the threshold, a further two thresholds are introduced above and below the first.

Once the decoder interpolates the bit-encoding value, it uses these three thresholds to assign one of four values to the bit-encoding value, representing unambiguous black, ambiguous dark gray, ambiguous light gray, or unambiguous white. The decoder therefore records two bits per output bit.

Once a given output bit's eight neighbours are available, the decoder uses a maximum-likelihood decoder to decode the correct value of the bit. A simpler decoder can be used if only two thresholds and three values (black, gray, and white) are used. Note also that bit values from the previous row and column are already resolved to a single bit.

Given the histograms shown in Section 12, typical thresholds might be 0.125, 0.25 and 0.5 respectively. These would vary with the dynamic range of the reader's actual imaging system, and might be generated dynamically based on the range of values observed during processing of the pilot, registration track, clock tracks and data.

The decoder buffers the output for each column to allow it to perform efficient word-oriented writes to external memory. It uses an address generator to compute the next output address for each data column as required, based on block number, column number, row number and word size.

As described earlier, the decoder is able to detect from the pilot when block space is 180 degrees rotated with respect to scan space, i.e. when blocks are being scanned from top to bottom rather than from bottom to top. When this is the case the decoder reverses the bit order of output words, and the address generator generates output addresses in reverse order. After raw data decoding is completed, the decoder moves the raw data in external memory so that its beginning is properly aligned.

Depending on the characteristics of the reader, both the spatial sampling period of the scan and the rotation of the block in scan space may vary due to non-linearities in the reader's mechanical transport. Since the transform which transforms block space to scan space may vary from one scanline to the next, the decoder re-computes the transform (and its corresponding deltas) for each scanline of each block, as described in Section 5.

3.2 Fault-Tolerant Data Layer Decoding

Decoding of the fault-tolerant data layer consists of two repeated steps: decoding of bitstream parameters, followed by decoding of the corresponding bitstream. As shown in FIG. 9, these are repeated for each encoded bitstream until the number of raw blocks is exhausted.

The design of the Mnem decoder includes optional hardware support for these decoding functions. However, since they are not required to be performed in real time during scanning, they can also be performed by software.

3.2.1 Decode Bitstream Parameters

As described earlier, in the fault-tolerant data layer the first and last column of each block encodes the parameters of the bitstream with a CRC, replicated as many times as will fit.

During scanline decoding, the decoder writes data from these columns to a contiguous area of external memory which is separate from the main data area.

In preparation for redundancy decoding each bitstream, the decoder processes the bitstream parameter data sequentially to obtain a good bitstream size for that bitstream. The decoder uses the first bitstream size which has a good CRC, and ignores the rest. If a good bitstream size cannot be obtained then the decoder signals an error for that stream. The process is shown in FIG. 10.

3.2.2 Decode Bitstream

Having obtained a good bitstream size, the decoder computes the corresponding number of Reed-Solomon codewords and Mnem blocks. As described earlier, the number of codewords equals the interleave factor.

The decoder uses an address generator to generate the addresses of interleaved symbols within a codeword, allowing it to interleave each codeword as it reads the codeword from external memory and de-interleave it as it writes it back. It uses a Reed-Solomon decoder to decode the codeword, and only writes the codeword back to external memory if it contains corrected errors. The process is shown in FIG. 11.

4. Track Data Clocks

The decoder continuously tracks the two data clocks throughout the subsequent decoding stages. This includes computing the intersection point of each scanline with the centre of each data clock track.

The scan-space y coordinate of the intersection point is simply the y coordinate of the scanline. Similarly, the block-space x coordinate of the intersection point is simply the x coordinate of the clock track.

The decoder uses a PLL to track each data clock. The block-space y coordinate of the intersection point is proportional to the phase θ_(c) of the clock:

$\begin{matrix} {y = \frac{\theta_{c}}{\pi}} & \left( {{EQ}\mspace{14mu} 53} \right) \end{matrix}$

Before the decoder acquires x registration, as described in Section 3.1.2, it predicts the scan-space x coordinate {tilde over (x)}′ of the intersection of the data clock with the new scanline from the intersection {tilde over (x)} with the previous scanline and the block rotation α:

{tilde over (x)}′={tilde over (x)}(1+sin α)  (EQ 54)

Once the decoder acquires x registration, it uses a PLL to track the alignment lines of each narrow data clock. The alignment PLL implements an accurate line-tracking servo with noise immunity. The decoder computes the scan-space x coordinate of the intersection point from the phase of the alignment PLL.

As described earlier, each data clock's two alignment lines are separated by a blank line. For the purposes of tracking the centre of the data clock from one scanline to the next, the alignment lines are treated as two ticks of a clock orthogonal to the data clock. On each new scanline, the decoder iterates each alignment PLL across the two clock ticks, i.e. over k pixels corresponding to a phase distance of about 3π or one-and-a-half clock cycles:

$\begin{matrix} {k = \left\lceil \frac{3\; \pi}{\delta} \right\rceil} & \left( {{EQ}\mspace{14mu} 55} \right) \end{matrix}$

where δ is the phase difference corresponding to one scan-space unit (EQ 31).

Before iterating the alignment PLL, the decoder copies the clock's initial phase θ_(l0)′ from the final phase θ_(l) of the previous scanline, adjusted to account for the approximately 3π phase difference, and for the estimated phase error between one scanline and the next due to the block rotation α:

θ_(l)′=θ_(l)+δ(k+sin α)  (EQ 56)

If the maximum block rotation α_(max) is small, then the effect of block rotation can be safely ignored.

The decoder preserves the alignment PLL's loop filter context (as described in Section 6) from one scanline to the next.

To initialise the alignment PLL immediately after the acquisition of x registration, the decoder computes the integer scan-space x coordinate {tilde over (x)}_(l0)′ and phase θ_(l0)′ of the first pixel used to update the PLL.

The centre of the first alignment line has a defined alignment phase θ_(l0) of zero:

θ_(l0)=0  (EQ 57)

The centre of the data clock track has a fixed alignment phase θ_(lc) derived from the width of the clock track and a clock tick:

$\begin{matrix} {\theta_{lc} = {\pi \left( {W_{c} - \frac{\left( {W_{ct} - 1} \right)}{2}} \right)}} & \left( {{EQ}\mspace{14mu} 58} \right) \end{matrix}$

The fractional scan-space x coordinate {tilde over (x)}_(l0) of the centre of the first alignment line is given by:

$\begin{matrix} {{\overset{\sim}{x}}_{l\; 0} = {{\overset{\sim}{x}}_{c} - \frac{\left( {\theta_{lc} - \theta_{l\; 0}} \right)}{\delta}}} & \left( {{EQ}\mspace{14mu} 59} \right) \end{matrix}$

Since the alignment PLL is updated with pixels with integer x coordinates, the decoder computes the integer scan-space x coordinate {tilde over (x)}_(l0)′ of the first pixel

{tilde over (x)} _(l0) ′=└{tilde over (x)} _(l0)+0.5┘  (EQ 60)

and hence its phase θ_(l0)′:

θ_(l0)′=θ_(l0)+δ({tilde over (x)} _(l0) −{tilde over (x)} _(l0))  (EQ 61)

Given the scan-space x coordinate {tilde over (x)}_(l) and phase θ_(l) of the final pixel used to update the alignment PLL on a given scanline, the decoder computes the scan-space x coordinate {tilde over (x)}′ of the intersection of the data clock with the scanline from the known phase θ_(lc) of the centre of the clock track:

$\begin{matrix} {{\overset{\sim}{x}}^{\prime} = {{\overset{\sim}{x}}_{l} + \frac{\left( {\theta_{lc} - \theta_{l}} \right)}{\delta}}} & \left( {{EQ}\mspace{14mu} 62} \right) \end{matrix}$

For the purpose of updating the data clock PLL, the decoder interpolates the pixels at └{tilde over (x)}′┘ and └{tilde over (x)}′┘+1, using a linear interpolation factor {tilde over (x)}′−└{tilde over (x)}′┘, to produce the input sample to the data clock PLL. If the maximum block rotation α_(max) is small, then the pixel at └{tilde over (x)}′┘ can be used directly rather than interpolating adjacent pixels.

When the decoder iterates the alignment PLL, it starts a fixed scan-space distance from the integer coordinate of the centre of the data clock. If the integer coordinate of centre of the data clock changes from one scanline to the next, then the decoder adjusts the initial phase of the alignment PLL accordingly, i.e. by ±δ.

5. Block Space to Scan Space Transform

The general affine transform relating block space to scan space is composed of a scale, a rotation and a translation.

The horizontal and vertical sampling rates are assumed to be equal. Actual deviations in the scanline period have little effect since all operations other than interpolation are relative to the current scanline.

FIG. 12 shows a rotated block in scan space.

In block space, let the two data clock tracks intersect the current scanline at P_(a) and P_(b):

P_(a)=(x_(a),y_(a),1)^(T)  (EQ 63)

P_(b)=(x_(b),y_(b),1)^(T)  (EQ 64)

and correspondingly in scan space:

{tilde over (P)}_(a)=({tilde over (x)}_(a),{tilde over (y)}_(s),1)^(T)  (EQ 65)

{tilde over (P)}_(b)=({tilde over (x)}_(b),{tilde over (y)}_(s),1)^(T)  (EQ 66)

where {tilde over (y)}_(s) is the y coordinate of the current scanline.

The transform M relating block space to a scan space is:

$\begin{matrix} {M = \begin{bmatrix} {S\; \cos \; \alpha} & {S\; \sin \; \alpha} & T_{x} \\ {{- S}\; \sin \; \alpha} & {S\; \cos \; \alpha} & T_{y} \\ 0 & 0 & 1 \end{bmatrix}} & \left( {{EQ}\mspace{14mu} 67} \right) \end{matrix}$

where S is the scale factor and α is the block rotation.

Transforming a known point allows us to solve for T_(x) and T_(y):

$\begin{matrix} {{\overset{\sim}{P}}_{a} = {M \cdot P_{a}}} & \left( {{EQ}\mspace{14mu} 68} \right) \\ {\begin{bmatrix} {\overset{\sim}{x}}_{a} \\ {\overset{\sim}{y}}_{a} \\ 1 \end{bmatrix} = \begin{bmatrix} {{S\; \cos \; \alpha \; x_{a}} + {S\; \sin \; \alpha \; y_{a}} + T_{x}} \\ {{{- S}\; \sin \; \alpha \; x_{a}} + {S\; \cos \; \alpha \; y_{a}} + T_{y}} \\ 1 \end{bmatrix}} & \left( {{EQ}\mspace{14mu} 69} \right) \\ {T_{x} = {{\overset{\sim}{x}}_{a} - {S\; \cos \; \alpha \; x_{a}} - {S\; \sin \; \alpha \; y_{a}}}} & \left( {{EQ}\mspace{14mu} 70} \right) \\ {T_{y} = {{\overset{\sim}{y}}_{a} + {S\; \sin \; \alpha \; x_{a}} - {S\; \cos \; \alpha \; y_{a}}}} & \left( {{EQ}\mspace{14mu} 71} \right) \end{matrix}$

Define orthogonal x and y displacement vectors in block space:

d_(x)=[1,0,0]^(T)  (EQ 72)

d_(y)=[0,1,0]^(T)  (EQ 73)

Transform into scan space:

{tilde over (d)}_(x) =M·d _(x)  (EQ 74)

{tilde over (d)}_(y) =M·d _(y)  (EQ 75)

{tilde over (d)}_(x)=[S cos α,−S sin α,0]^(T)  (EQ 76)

{tilde over (d)}_(y)=[S sin α,S cos α,0]^(T)  (EQ 77)

As shown in FIG. 12, let:

$\begin{matrix} {d = {x_{b} - x_{a}}} & \left( {{EQ}\mspace{14mu} 78} \right) \\ {e = {y_{a} - y_{b}}} & \left( {{EQ}\mspace{14mu} 79} \right) \\ {f^{2} = {d^{2} + e^{2}}} & \left( {{EQ}\mspace{14mu} 80} \right) \\ {{\overset{\sim}{f} = {{\overset{\sim}{x}}_{b} - {\overset{\sim}{x}}_{a}}}{{Then}\text{:}}} & \left( {{EQ}\mspace{14mu} 81} \right) \\ {{\sin \; \alpha} = \frac{e}{f}} & \left( {{EQ}\mspace{14mu} 82} \right) \\ {{\cos \; \alpha} = \frac{d}{f}} & \left( {{EQ}\mspace{14mu} 83} \right) \end{matrix}$

And the scale factor S relating block space to scan space is:

$\begin{matrix} {{S = \frac{\overset{\sim}{f}}{f}}{{Hence}\text{:}}} & \left( {{EQ}\mspace{14mu} 84} \right) \\ {{\overset{\sim}{d}}_{x} = \left\lbrack {\frac{\overset{\sim}{f}\; d}{f},\frac{\overset{\sim}{f}\; e}{f},0} \right\rbrack^{T}} & \left( {{EQ}\mspace{14mu} 85} \right) \\ {{\overset{\sim}{d}}_{y} = \left\lbrack {\frac{\overset{\sim}{f}\; e}{f},\frac{\overset{\sim}{f}\; d}{f},0} \right\rbrack^{T}} & \left( {{EQ}\mspace{14mu} 86} \right) \end{matrix}$

Define the bit-encoding location of the j^(th) bit of the i^(th) data column:

P _(d)(i,j)=P _(d0) +[i,j,0]^(T)  (EQ 87)

{tilde over (P)}_(d)(i,j)=M·P _(d)(i,j)  (EQ 88)

Its scan-space transform can be decomposed as follows:

{tilde over (P)}_(d)(i,j)=M·P _(d0) +M·[i,0,0]^(T) +M·[0,j,0]^(T)  (EQ 89)

{tilde over (P)}_(d)(i,j)=M·P _(d0) +i{tilde over (d)} _(x) +j{tilde over (d)} _(y)  (EQ 90)

This final form is suitable for incrementally computing {tilde over (P)}_(d) for successive columns, since i increases by one for each successive column, and j changes by a maximum of one for each successive column.

6. Clocking and PLLs

Phase-locked loops (PLLs) are used variously to lock onto the pilot, lock onto the horizontal registration clock, track the vertical data clocks, and track the vertical data clocks' alignment lines.

All of the clocks have the same period, and the largest source of clock frequency variation is the rotation of the block in scan space. The PLLs are therefore required to support a relatively small lock range which is proportional to the sine of the maximum block rotation.

The two primary purposes of the PLLs are (a) to suppress relatively low-frequency noise due to surface damage and contamination; and (b) to track the clocks in the presence of low-frequency variation, for example due to the vagaries of the media transport mechanics, and without exact knowledge of block rotation and scale.

Different strategies may be employed for effectively imaging a Mnem area. These typically reflect trade-offs between sampling rate and sample resolution for a given data rate. At one extreme, multi-level samples of the image can be taken at close to the Nyquist rate of the image. At the other extreme, bi-level samples of the image can be taken at a correspondingly higher rate. Because of the potentially high density of a Mnem data grid, it is more practical to perform multi-level Nyquist-rate sampling.

The possibility of surface contamination and damage motivates the use of a PLL which is resistant to missing pulses. This in turn motivates the use of a level-sensitive phase detector rather than an edge-sensitive phase detector.

The Nyquist rate image sampling frequency is at least twice the frequency of the data grid. Since the various clocks' ticks are defined on odd coordinates, the sampling frequency is at least four times the clock frequency. In a Mnem reader the samples are intrinsically low-pass filtered by the optics and by the two-dimensional extent of each image sensor element. However, due to the sharp edges of the clock ticks, frequencies above the clock frequency but below half the sampling rate are likely to be present, and these can benefit from further digital-domain low-pass filtering. More generally, it is useful to band-limit the input signal to a PLL to the frequency range of interest. Depending on the design of the PLL phase detector, it may also be necessary to expand the dynamic range of the input samples to the available dynamic range, to normalise the amplitude of the input signal.

The use of an image sensor with an on-board analog-to-digital converter (ADC) and a digital interface implies a PLL with a digital design. However, with Nyquist-rate sampling, the sampling rate is too low for a conventional binary digital PLL design. Instead a digital version of a linear PLL is appropriate, operating on multi-level signals.

The pilot clock PLL is initially unlocked. A PLL design which locks quickly is therefore desired, since this allows the size of the pilot lead-in to be minimised. This motivates, but does not necessitate, the use of a phase detector which computes the phase error directly, as discussed further below. The size of the lead-in can ultimately be tuned to match the performance of the pilot clock PLL. Similar reasoning applies to the initially unlocked registration clock PLL, although the registration clock is typically not as size-constrained as the pilot. The pilot and registration clock PLLs contrast with the data clock and alignment PLLs which are both initially locked. For similar reasons it is possible to use different loop filter parameters for these various PLLs.

6.1 Discrete-Time Digital PLL

FIG. 13 shows the generic structure of a discrete-time digital PLL with a first-order loop filter, described for example in Best, R. E., Phase-Locked Loops, Design, Simulation, and Applications, Fifth Edition, McGraw-Hill 2003. The digital phase detector 700 generates an output signal u_(d) which is proportional to the phase difference θ_(e) between the phase θ_(l) of the input reference signal u₁ and the phase θ₂ of the oscillator output signal u₂. The digital loop filter 701 suppresses input signal noise manifest in the phase detector output, and extracts the DC component of the phase detector output as the phase error (although this latter function is sometimes performed by a separate low-pass filter, as described for example in Abramovitch, D., Phase-Locked Loops: A Control Centric Tutorial, Proceedings of the American Control Conference 2002). The loop filter output u_(f) provides the control input to the digital oscillator 702, pulling it from its central frequency ω₀ towards lock with the reference signal, where the frequency ω₂ and phase θ₂ of the oscillator match the frequency ω₁ and phase θ₁ of the reference signal. The PLL is clocked by the sampling clock with period T_(s), obtained from the ADC 703.

For each input sample u₁(n), the PLL is updated as follows:

u _(d)(n)←K _(d)PhaseDetector(u ₁(n),u ₂(n))  (EQ 91)

u _(f)(n)←−a ₁ u _(f)(n−1)+b ₀ u _(d)(n)+b ₁ u _(d)(n−1)  (EQ 92)

θ₂(n+1)←θ₂(n)+(ω₀ +K ₀ u _(f)(n))T _(s)  (EQ 93)

u ₂(n+1)←cos(θ₂(n+1)  (EQ 94)

u _(d)(n−1)←u _(d)(n)  (EQ 95)

u _(f)(n−1)←u _(f)(n)  (EQ 96)

θ₂(n)←θ₂(n+1)  (EQ 97)

u ₂(n)←u ₂(n+1)  (EQ 98)

where K_(d) and K₀ represents the phase detector and oscillator gains respectively.

The first-order loop filter parameters a₁, b₀ and b₁ are calculated to provide the desired PLL performance in the presence of noise as described for example in Best, R. E., Phase-Locked Loops, Design, Simulation, and Applications, Fifth Edition, McGraw-Hill 2003.

For Mnem decoder PLLs the oscillator phase θ₂ is proportional to block-space displacement s:

s=θ ₂/π  (EQ 99)

6.2 Phase Detection Approaches

The input signal u₁ and output signal u₂ are modelled as follows:

u ₁(n)=A sin(ω₁ x+θ ₁)  (EQ 100)

u ₂(n)=cos(ω₂ x+θ ₂)  (EQ 101)

where:

x=nT_(s)  (EQ 102)

The simplest phase detector is a multiplier. The product of the reference signal u₁ and oscillator signal u₂ has a DC level which is proportional to the sine of the phase difference between them:

∫u₁(n)u₂(n)dn∝ sin(ω₁x−ω₂x+θ₁−θ₂)  (EQ 103)

When the PLL is frequency locked, the reference frequency ω₁ and oscillator frequency ω₂ are the same, and the DC level is proportional to the sine of the phase error θ_(e) alone:

∫u ₁(n)u ₂(n)dn∝ sin(θ₁−θ₂)=sin(θ_(e))  (EQ 104)

For small phase errors the sine of the phase error approximates the phase error itself, and this is the basis for the linearised model of the PLL:

u _(n) =K _(d) sin(θ_(e))→K _(d)θ_(e) as θ_(e)→0  (EQ 105)

When the PLL is not frequency locked, then the difference between the reference frequency ω₁ and oscillator frequency ω₂ contributes to the phase error, pulling the oscillator towards lock.

A more economical square-wave oscillator is often used place of a sinusoidal oscillator in conjunction with a multiplier phase detector, since the fundamental component of the Fourier series expansion of the square wave is proportional to the desired cosine term, and higher-frequency components are eliminated by the loop filter. However, for close to Nyquist-rate sampling rates, a PLL with a sinusoidal oscillator performs better.

The phase detector benefits from the availability of both in-phase I and quadrature Q signals for both the reference input and the oscillator output:

I ₁(n)=A cos(ω₁ x+θ ₁)  (EQ 106)

Q ₁(n)=u ₁(n)=A sin(ω₁ x+θ ₁)  (EQ 107)

I ₂(n)=u ₂(n)=cos(ω₂ x+θ ₂)  (EQ 108)

Q ₂(n)=sin(ω₂ x+θ ₂)  (EQ 109)

Minimally this allows the phase detector to compute the instantaneous sine of the phase error, which for small phase errors approximates the phase error itself (as noted above):

Q ₁ I ₂ −I ₁ Q ₂ =A sin(θ₁−θ₂)=A sin(θ_(e))  (EQ 110)

In general, when the phase detector outputs a signal proportional to the sine of the phase error, the effective phase detector gain K_(d)′ is proportional to the sinc of the phase error, which diminishes to zero as the phase error approaches its maximum of ±π:

$\begin{matrix} {K_{d}^{\prime} = {K_{d}\frac{\sin \left( \theta_{e} \right)}{\theta_{e}}}} & \left( {{EQ}\mspace{14mu} 111} \right) \end{matrix}$

For larger phase errors, we are therefore motivated to compute the phase error directly. When the phase detector computes the phase error directly, the effective phase detector gain is independent of phase error, allowing more rapid phase lock.

The phase detector can compute the phase error directly as follows:

$\begin{matrix} {{{Q_{1}Q_{2}} + {I_{1}I_{2}}} = {{A\; {\cos \left( {\theta_{1} - \theta_{2}} \right)}} = {A\; {\cos \left( \theta_{e} \right)}}}} & \left( {{EQ}\mspace{14mu} 112} \right) \\ {\frac{{Q_{1}I_{2}} - {I_{1}Q_{2}}}{{Q_{1}Q_{2}} + {I_{1}I_{2}}} = {\frac{A\; {\sin \left( \theta_{e} \right)}}{A\; {\cos \left( \theta_{e} \right)}} = {\tan \left( \theta_{e} \right)}}} & \left( {{EQ}\mspace{14mu} 113} \right) \\ {{{atan}\left( {\tan \left( \theta_{e} \right)} \right)} = \theta_{e}} & \left( {{EQ}\mspace{14mu} 114} \right) \end{matrix}$

Since in-phase and quadrature signals are generally not directly available for the reference input, a Hilbert transformer can be used to generate one from the other (see for example Best, R. E., Phase-Locked Loops, Design, Simulation, and Applications, Fifth Edition, McGraw-Hill 2003, and Stein, J. Y., Digital Signal Processing, Wiley-Interscience, 2000). Since the frequency range of the Mnem PLLs is highly constrained, a simpler π/2 delay filter may also be used.

Many other phase detector approaches are possible, including interpolation-based detection of zero crossings, and interpolation-based detection of peaks, the design of which has been disclosed in a series of Granted patents and pending patent applications listed in the cross references above.

7. Reader Architecture

For the purposes of reader and decoder design, it is assumed that a card-based Mnem medium is transported past a linear image sensor at constant speed, the linear image sensor scans the card's Mnem area line by line, and the decoder decodes the scan data in real time during the scan.

FIG. 14 shows a high-level block diagram of a Mnem reader. The reader contains an imaging system, a transport system, an integrated Mnem decoder, external memory for decoded data, and a host controller.

The reader's imaging system consists of illumination LEDs 710 and a linear image sensor 711. The reader's media transport system consists of dual media detectors 712 and a transport motor 713. Once the controller detects card insertion via the media detectors, it generates scanline clock pulses for the duration of the scan which control the exposure of the image sensor and the speed of the motor.

Each scanline clock pulse signals the image sensor to begin acquisition of the scanline. The exposure period is pre-configured in the image sensor. On each clock pulse the decoder also generates a level signal which switches on the illumination LEDs for the duration of the exposure period.

During the scan the decoder 714 writes decoded raw data to external memory 715. After the scan is complete the decoder optionally performs redundancy decoding to correct errors in the raw data. Alternatively the host controller 716 performs its own redundancy decoding.

The decoder informs the host controller of decoding completion via an interrupt (if enabled). Alternatively the host controller polls a decoder status register.

After decoding completion the host controller reads the decoded data from external memory for application-specific use.

The host controller configures operation of the decoder via a set of configuration registers. Configuration parameters include the variable parameters defined in Table 1, as well as the image sensor exposure period and decoding options. Allowable parameter ranges are decoder-specific.

7.1 Data Rates

Given a real-space transport speed v_(r) in the direction normal to the scanline, the approximate block-space transport speed v_(m) is given by:

v_(m)=v_(r)R  (EQ 115)

where R is the real-space to block-space scale factor.

The block-space data rate r_(d) (in bits per second) is then given by:

r_(d)=W_(m)v_(m)  (EQ 116)

where W_(m) is the block-space width of the Mnem area.

This is the rate at which the decoder generates bit values, and represents the average data rate between the decoder and external memory during raw decoding.

The scan-space transport speed {tilde over (v)}_(s) (in scanlines per second) is given by:

{tilde over (v)}_(s)=v_(m)N  (EQ 117)

where N is the sampling rate.

The scan-space data rate {tilde over (r)}_(s) (in samples per second) is given by:

{tilde over (r)}_(s)={tilde over (W)}_(s){tilde over (v)}_(s)≅r_(d)N²  (EQ 118)

where {tilde over (W)}_(s) is the scanline width (EQ 24).

This is the rate at which the decoder consumes samples from the image sensor, and represents the average date rate between the image sensor and the decoder during the scan.

Assuming the decoder supports a maximum scan data rate {tilde over (r)}_(s), the reader can adjust the transport speed v_(r) for a given scan width {tilde over (W)}_(s), to satisfy EQ 118. This implies different static settings for readers configured for different media widths, and different dynamic settings for readers which support multiple media widths.

The minimum total scan time t_(scan) for a Mnem area height H_(m) is given by:

$\begin{matrix} {t_{scan} = \frac{H_{m}}{v_{m}}} & \left( {{EQ}\mspace{14mu} 119} \right) \end{matrix}$

This can be used to compute the velocity (and hence scan data rate) required to provide a particular desired scan time.

7.2 Mechanical Considerations

Scan transport only commences once the two media detectors simultaneously detect the presence of a card. This minimises the initial rotation of the card, and minimises progressive rotation due to collision between the card and the internal side walls of the transport path.

As shown FIG. 15, if the image sensor is placed close to the transport roller 717, then it may also be used for detection of the media 718 as it moves in a transport direction, as shown by the arrow 719. This has the additional advantage of allowing different media widths to be detected.

If the transport roller is sprung, e.g. to comply with different media thicknesses, then placing the image sensor close to the roller also minimises the required depth of field.

The reader may optionally incorporate a motion sensor, such as a texture displacement sensor, as described for example in Gordon, G., Seeing eye mouse for a computer system, U.S. Pat. No. 6,433,780, to allow it to synchronise scanning with the actual motion of the medium.

7.3 Imaging Considerations

The motion-induced block-space blur radius b_(v) is a function of the transport speed v_(m) and the exposure time t_(e):

b_(v)=v_(m)t_(e)  (EQ 120)

Assuming a maximum allowed block-space blur radius b_(max), and a blur radius b_(f) associated with the imaging optics, the exposure time is then bounded as follows:

$\begin{matrix} {{b_{f} + b_{v}} \leq b_{\max}} & \left( {{EQ}\mspace{14mu} 121} \right) \\ {t_{e} = {\frac{b_{v}}{v_{m}} \leq \frac{b_{\max} - b_{f}}{v_{m}}}} & \left( {{EQ}\mspace{14mu} 122} \right) \end{matrix}$

Since the allowed motion blur radius is bounded by the size of a block-space unit, the exposure time is a bounded by the block-space line time or N times the scanline time:

$\begin{matrix} {{t_{e} \leq \frac{1}{v_{m}}} = \frac{N}{{\overset{\sim}{v}}_{s}}} & \left( {{EQ}\mspace{14mu} 123} \right) \end{matrix}$

In practice, to allow image sensor read-out at least once per scanline, and assuming no buffering in the image sensor, the exposure time is bounded by the scanline time less the read-out time t_(i):

$\begin{matrix} {t_{i} = \frac{{\overset{\sim}{W}}_{s}}{r_{i}}} & \left( {{EQ}\mspace{14mu} 124} \right) \\ {t_{e} \leq {\frac{1}{{\overset{\sim}{v}}_{s}} - t_{i}}} & \left( {{EQ}\mspace{14mu} 125} \right) \end{matrix}$

where r_(i) is the image sensor data read-out rate (in samples per second).

As discussed in Section 6, the reader uses the imaging system to perform multi-level Nyquist-rate sampling of the Mnem area. The sampling rate N is therefore normally chosen between 2 and 3.

The Kodak KLI-8811 8800 Element Linear CCD Image Sensor Performance Specification, Revision 0, Oct. 3, 2000 is an example of a linear image sensor suitable for imaging a Mnem area with a data density R of 1600 per inch, as supported by Memjet-based printers described in more detail in Section 9 below. It has a width of 8800 pixels, each 7 μm wide, giving a sampling rate N of approximately 2.3, and supporting a scan width {tilde over (W)}_(s) up to approximately 62 mm.

7.4 Encoding and Printing Considerations

When the reader is part of a device which is also capable of printing Mnem areas, it can be useful to combine the Mnem encoding and decoding functions in a single integrated encoder/decoder.

Encoding is the inverse process of decoding. It consists of a redundancy encoding phase, following by a raw data encoding phase. The raw data encoding phase usefully takes place in real time during printing, to eliminate the need for buffer memory for the rendered Mnem area image.

As noted elsewhere, scanline decoding assumes and therefore requires block-space uniformity, at least locally. This in turn requires a constant print speed.

When the reader is part of a device which is capable of printing Mnem areas, it can also be useful to combine the linear image sensor and the printhead into a single integrated device. This is efficacious because the two devices have a similar form factor, they are usefully co-located in the host device since printing and scanning can share the same media transport, the linear image sensor adds only a small overhead to the printhead silicon, and device packaging and handling costs are effectively halved.

Section 8 describes a Memjet printhead with an integrated row of active pixel sensors, details of which are provided in a series of granted patents and pending patent applications, including U.S. Pat. No. 6,302,528 entitled “Thermal actuated ink jet printing mechanism”. All other patents and pending applications on this technology are provided in the cross-references section above. Several high-sensitivity active pixel designs which may be adapted for integration with a Memjet printhead are described in a series of patent applications U.S. Ser. No. 10/778,057, U.S. Ser. No. 10/778,061, U.S. Ser. No. 10/778,062, U.S. Ser. No. 10/778,063, U.S. Ser. No. 10/778,059, U.S. Ser. No. 10/778,060, U.S. Ser. No. 10/778,058, U.S. Ser. No. 10/778,056 filed 17 Feb. 2004, including an application entitled “Image sensor with digital framestore,” the details of all other applications in this series are provided in the cross-references section above. The sampling rate N is 2.5 in the arrangement shown.

8. Printhead with Integral Image Sensor Architecture

Mnem is a robust two-dimensional optical encoding scheme for storing digital data on physical surfaces. Its data capacity scales linearly with surface area. It fundamentally supports read-only (RO) and write-once read-many (WORM) applications, and includes the ability to append data. It incorporates optional fault tolerance to cope with real-world surface degradation.

Mnem is suitable for inkjet printing. When printed using an invisible ink such as an infrared absorptive or fluorescent ink, Mnem-encoded data may be superimposed on visible text and colour graphics. This allows, for example, a digital negative of a photograph to be invisibly superimposed on a colour print of the photograph.

When a Mnem reader is part of a device which is capable of printing Mnem areas, it is useful to combine the linear image sensor and the printhead into a single integrated device. This is efficacious because the two devices have a similar form factor, they are usefully co-located in the host device since printing and scanning can share the same media transport, the linear image sensor adds only a small overhead to the printhead silicon, and device packaging and handling costs are effectively halved.

If the printhead is only used for printing Mnem areas, then only a single row of nozzles is required.

If Mnem areas are superimposed on human-readable information such as text, graphics and images, then an invisible ink must be used. In Mnem areas are only printed in isolation, then either a visible or an invisible ink may be used.

If the Mnem printer is also used for printing human-readable information, then additional rows of nozzles must be provided for the corresponding monochrome or coloured inks Memjet printheads, such as those discussed in Section 9 below, typically provide at least five rows of nozzles for jetting cyan, magenta, yellow, black and infrared inks

8.1 Memjet Printhead with Integral Image Sensor

FIG. 16 shows a detailed physical view of a Memjet printhead IC with an integral image sensor. For simplicity the figure only shows a single row of 1600 dpi nozzles 600, mounted adjacent associated actuators and drive circuitry shown generally at 601. Note that because the 32-micron width of each nozzle unit cell exceeds the 16-micron dot pitch required for 1600 dpi printing, each row of nozzles is composed of two staggered half-rows 602, 603. The Mnem sampling rate N is 2.5 in the arrangement shown.

Although a Mnem area may utilise a single printed dot to represent a single encoded bit, it may also utilise more than one printed dot to represent a single encoded bit. For example, a Mnem area may utilise a 2×2 array of printed dots to represent a single bit. Thus if the printer resolution is 1600 dpi, the Mnem area resolution is only 800 dpi. In certain applications, reducing the print resolution of a Mnem area may provide more robust Mnem performance, such as in the presence of particular sources of surface degradation or damage.

If the Mnem area resolution is lower than the printer resolution, then the ratio of the pixel count to the nozzle count can be reduced accordingly, and larger pixel sensors can be employed. For example, in the case of the Memjet printhead shown in FIG. 16, a 12.8 micron pixel sensor can be utilised in place of two 6.4 micron pixel sensors.

FIG. 17 shows a logical view of the IC of FIG. 16. For simplicity the figure only shows one half-row of Memjet nozzles.

The IC exposes a number of status and configuration registers via a low-speed serial (LSS) link. These allow image capture and printing parameters to be configured and status information to be read back by an external controlling device.

8.2 Linear Image Sensor

The linear image sensor consists of an array of CMOS active pixel sensors (APSs) 604. Each pixel sensor may utilise a typical APS circuit as shown in FIG. 18 and discussed further below. For simplicity the figure only shows one row of pixel sensors.

In a monochrome linear image sensor only one row 605 of pixel sensors 604 is required. For example, if the sensor is only used for reading Mnem areas, then only one row of pixel sensors is required. In a colour linear image sensor multiple rows of pixel sensors may be utilised, and each row may have its own filter to select a particular wavelength range, either corresponding to a spectral colour such as red, green or blue, or to the absorption spectrum of the ink used to print the Mnem area, which may be an infrared ink. Colour filters may also be spatially interleaved within a single row to reduce the number of rows needed for colour scanning, with some loss in scan resolution. For example, the image sensor may contain a single row with red, green and blue filters, and a second row with an infrared filter.

Scan imaging typically utilises artificial illumination since it takes place inside a reader or scanner. Depending on application, the illumination may be broadband or narrowband.

Rather than (or in addition to) utilising spectral filters, multi-spectral imaging may be performed using multiple spectral light sources, for example using red, green, blue and infrared light sources. These can be strobed in rapid succession, interleaved with image readout from a single row of pixel sensors, to achieve multi-spectral imaging using only a single row of pixel sensors. Alternatively, multiple rows of pixel sensors can still be utilised, but each row can be exposed selectively in turn, in synchrony with the strobing of one spectral light source. In this case each pixel sensor may utilise a typical shuttered APS circuit as shown in FIG. 19 and discussed further below. This can have the advantage that almost simultaneous exposure of all spectral rows can be achieved, since the shuttered pixel sensors can decouple fast exposure from relatively slower readout.

A reader or scanner can support multiple scanning modes, selectable under user control, e.g. to scan colour images, scan Mnem areas, etc. A reader or scanner can also be adaptive, automatically detecting the presence of a Mnem area via a test scan in the infrared spectrum and as a result switching from colour scanning to Mnem area scanning.

The linear image sensor includes a clock generator 610 which accepts an external master clock signal (MClk) and generates a pixel clock (PClk). It may incorporate a programmable PLL and/or a clock divider or multiplier to allow it to flexibly generate the pixel clock from the master clock.

The linear image sensor operates under the control of a pixel timing and control block 611. Its configuration registers allow a number of image capture parameters to be set, including the master clock multiplier, the exposure time, and the analog offset and gain. It typically operates at the pixel clock rate or some integer multiple thereof.

The pixel control block is responsive to signals on the Reset, Expose and Read input pins to respectively reset, expose and read out the pixel sensor array. These control signals are also register-mapped and available from a register 612 via an LSS interface 613. The control block generates the appropriate timing and control signals to the pixel sensor array.

On reset, the pixel control block asserts a Reset signal to the entire pixel sensor array.

On expose, the pixel control block starts a timer with an initial value of the exposure time. If the pixel sensor array utilises shuttered pixel sensors, then the pixel control block asserts a Transfer signal for the duration of the exposure timer. If the pixel sensor array utilises non-shuttered pixel sensors, then the pixel control block may be configured to automatically trigger readout on expiry of the exposure timer.

On read, the pixel control block sequentially reads out the values of all of the pixel sensors in the array. If the linear image sensor contains more than one row of pixel sensors, as discussed earlier, then it may include a row address decoder (not shown in FIG. 17). The pixel control block generates each row address in turn, and the row address decoder decodes the row address into a unique Row Select signal. Each pixel sensor in the selected row asserts its value onto its corresponding column bus. Within each row, the pixel control block generates each column address in turn, and a column address decoder 614 decodes the column address into a unique Column Select signal which multiplexes a particular column bus onto the output stage. The output stage consists of a programmable gain amplifier (PGA) 615 followed by an analog-to-digital converter (ADC) 616. The PGA provides digital control over analog offset and gain. The ADC produces the digital pixel value which is subsequently output on a pixel-wide parallel output pins (P). The ADC typically has 8-bit or greater precision.

The pixel control block asserts the frame valid signal (FValid) on an output pin for the duration of the readout. Pixel values clocked by the pixel clock (PClk) during readout. The pixel clock is provided on the PClk output pin.

The pixel sensor array is also register-mapped via an address and data register. An individual pixel is read by writing its row and column address to the pixel address register and then reading the pixel data register.

The pixel control block supports two capture modes. In automatic mode the entire reset-expose-read cycle capture is triggered by an external line synchronisation signal (LsyncL). In manual mode each step in the capture cycle is triggered separately by its corresponding signal.

FIG. 18 shows a typical CMOS active pixel sensor, where M1 is the reset transistor, M3 is the output transistor, and M4 is the row-select transistor.

FIG. 19 shows a typical CMOS shuttered active pixel sensor, where the shuttering function is provided by the transfer transistor M2. Charge retention is provided by the parasitic capacitance at storage node X, represented by Cs. This can be augmented with explicit capacitance to increase charge retention. M2 is switched on by the Transfer signal for the duration of the pixel exposure period, after which the pixel value can be read out at leisure without contamination by further photodiode activity.

The design of an electronically-shuttered CMOS imager including enhancements to the typical shuttered APS design is described in more detail in, “Image sensor with digital framestore”, U.S. patent application Ser. No. 10/778,056 (Docket Number NPS047), filed 17 Feb. 2004, claiming priority from “Methods, systems and apparatus”, Australian Provisional Patent Application 2003900746 (Docket Number NPS041), filed 17 Feb. 2003.

8.3 Memjet Printhead

The Memjet printhead consists of an array of Memjet nozzles, each with a thermal bend or thermal bubble actuator as discussed in more detail in Section 9 below. Prior to the printing of a line of dots, the dot values for the line are shifted into a dot shift register 617 which has the same width as the line. The dot values are provided on a serial input pin (D) by the external host device, clocked by a serial clock (SrClk). On receipt of a line synchronisation signal (LsyncL), each dot value in the shift register is transferred to a dot latch associated with a corresponding nozzle. The fire enable signals for an entire line are contained in a fire shift register 618. This shift register contains a firing pattern which ensures that only a subset of nozzles fire simultaneously, to limit instantaneous power consumption. The shift register is clocked by the fire clock signal (FrClk) provided by the external host. Each nozzle's actuator is controlled by its corresponding dot value, its fire enable signal (Fr) derived from the fire shift register, and a pulse profile signal (Pr), and fires for a duration equal to the AND of these three signals.

The nozzle array is controlled by the nozzle timing and control block 619. The nozzle control block seeds the fire shift register with the firing pattern, and provides the pulse profile signal (Pr) during nozzle firing.

8.4 Multi-Segment Device

The IC is usefully designed so that multiple ICs can be abutted to form a single larger device with a correspondingly larger number of pixel sensors and nozzles. Linking Memjet printhead segments with this property are described in more detail in Section 9 below. The linking Memjet segment design is easily extended to include linking arrays of pixel sensors. Although the control and timing blocks of the IC are shown to the right of the pixel sensor and nozzle arrays in FIG. 17, they are physically laid out in the area below the pixel sensor and nozzle arrays when a linking design is desired.

Since both the pixel sensor array and nozzle array is displaced in the overlap region between two segments, hardware or software in the external controlling device must offset input image data and output print data in the overlap region according to the known transport velocity of the scan or print medium and the known array displacement.

FIG. 20 shows three IC segments abutted to form a wider multi-segment device. Each IC has a set of ID pins which allow it to be statically configured with a unique address on the low-speed serial (LSS) bus. Segment 0 is configured to generate the pixel clock (PClk) from the master clock (MClk). The remaining segments are configured to accept the pixel clock from segment 0 as their master clock and pixel clock.

The Reset and Expose signals are routed to all segments simultaneously, but the Read signal is not used. Instead, readout from a particular segment is requested by asserting the Read flag in its control register. The pixel data output pins (P) and frame valid output pin (FValid) are normally tristated and are only driven by a segment during pixel readout.

The line synchronisation (LsyncL), fire clock (FrClk), and serial clock (SrClk) signals are routed to all segments simultaneously. The dot data lines (D) provide serial dot data to each segment in parallel.

8.5 Fabrication and Housing

Memjet nozzles and actuators are fabricated using micro-electromechanical system (MEMS) fabrication techniques, as described in Section 9 below. Analog and digital electronic circuitry is fabricated using standard mixed-signal CMOS fabrication techniques. Ink channels etc. are fabricated using MEMS post-processing, also as described in Section 9 below.

Packaging of a Memjet printhead is described in Section 9 below. Post-processing and packaging of the IC for imaging purposes is discussed further here.

The linear image sensor is designed for 1:1 contact imaging. As such it requires per-pixel lensing to capture a reasonably sharp image of a scanline Contact imaging systems typically utilise gradient-index (GRIN) rod lens arrays described for example in Bell, C. J., “Gradient index lens array assembly comprising a plurality of lens arrays optically coupled in a lengthwise direction”, U.S. Pat. No. 6,011,888, issued 4 Jan. 2000, such as SELFOC™ arrays (Nippon Sheet Glass, Information Technology—Optoelectronics Products). They may also utilise clad fiber arrays (Schott A G, Leached Image Bundles), possibly with curved fiber ends for refractive focusing. Microlenses can also be applied at wafer scale as a post-processing step, where they are typically applied to increase effectively fill factor. This is described for example in Iwasaki, T. et al, “Method for producing a microlens array”, U.S. Pat. No. 5,298,366, issued 29 Mar. 1994 Rhodes, H. E., “Microlens array with improved fill factor”, U.S. Pat. No. 6,307,243, issued 23 Oct. 2001. However, they can also be stacked to support effective imaging (Voelker, R., M Eisner and K. J. Weible, “Miniaturized imaging systems”, Microelectronic Engineering 67-68 (2003) 461-472).

FIG. 21 shows the printhead IC 620 packaged and mounted for both printing or scanning a medium passing through the same transport mechanism. The IC has an ink supply molding 621 connected which connects to an ink supply (not shown). It also has a flexible circuit board (FCB) 622 which connects it electrically to a host device and power.

The IC is mounted in a cavity in a housing 623 which in turn mounts flush with a transport path. In use, droplets 631 are ejected along a droplet ejection path 624 and pass through an open slot 625 in the housing 623 to allow droplets to be deposited on a print medium 626 in the transport path.

An imaging path 627 passes through an array of focusing elements 628, such as a lens array, and a cover glass 629 to image the scan medium 626 in the transport path. An array of illumination LEDs 630 are mounted at an angle below the cover glass to provide illumination of the scanline.

9. Printer Architecture

Mnem areas are preferably printed by MEMJET™ printheads. The fabrication and operation of many different MEMJET™ printheads are comprehensively described in the above cross referenced patents and applications. However, in the interests of brevity, an overview of the printhead operation and basic nozzle structures are set out below.

9.1 Printhead Assembly

FIG. 22 is an exploded perspective of a typical MEMJET™ printhead. This particular printhead assembly is used in one of the Applicant's SOHO printers (see U.S. Ser. No. 11/014,769,U.S. Ser. No. 11/014,729,U.S. Ser. No. 11/014,743,U.S. Ser. No. 11/014,733,U.S. Ser. No. 11/014,755) but it will be appreciated that Mnem areas may be printed by the many other MEMJET™ printheads disclosed in the cross referenced patents and applications.

FIG. 22 actually shows the underside of the assembly to clearly depict the ink feed system through the components to the printhead integrated circuit 74. FIG. 23 is a cross section of the printhead assembly 22 in its assembled form and normal orientation. The assembly comprises an elongate upper member 62 which is configured to mount to the printer chassis via U-shaped clips 63.

The upper element 62 has a plurality of feed tubes 64 that are received within the outlets in the outlet molding 27 when the printhead assembly 22 secures to the main body 20. The feed tubes 64 may be provided with an outer coating to guard against ink leakage.

The upper member 62 is made from a liquid crystal polymer (LCP) which offers a number of advantages. It can be molded so that its coefficient of thermal expansion (CTE) is similar to that of silicon. It will be appreciated that any significant difference in the CTE's of the printhead integrated circuit 74 (discussed below) and the underlying moldings can cause the entire structure to bow. However, as the CTE of LCP in the mold direction is much less than that in the non-mold direction (˜5 ppm/° C. compared to ˜20 ppm/° C.), care must be take to ensure that the mold direction of the LCP moldings is unidirectional with the longitudinal extent of the printhead integrated circuit (IC) 74. LCP also has a relatively high stiffness with a modulus that is typically 5 times that of ‘normal plastics’ such as polycarbonates, styrene, nylon, PET and polypropylene.

As best shown in FIG. 23, upper member 62 has an open channel configuration for receiving a lower member 65, which is bonded thereto, via an adhesive film 66 (see FIG. 22). The lower member 65 is also made from an LCP and has a plurality of ink channels 67 formed along its length. Each of the ink channels 67 receive ink from one of the feed tubes 64, and distribute the ink along the length of the printhead assembly 22. The channels are 1 mm wide and separated by 0.75 mm thick walls.

The lower member 65 has five channels 67 extending along its length. Each channel 67 receives ink from only one of the five feed tubes 64, which in turn receives ink from respective ink storage reservoirs to reduce the risk of mixing different colored inks Adhesive film 66 also acts to seal the individual ink channels 67 to prevent cross channel mixing of the ink when the lower member 65 is assembled to the upper member 62.

A series of equi-spaced holes in five rows along the bottom of each channel 67 lead to holes 69 shown in the bottom surface of the lower member 65. An enlarged view of these holes 69 is shown in FIG. 24. The middle row of holes 69 extends along the centre-line of the lower member 65, directly above the printhead IC 74. Other rows of holes 69 on either side of the middle row need conduits 70 from each hole 69 to the centre so that ink can be fed to the printhead IC 74.

The printhead IC 74 is mounted to the underside of the lower member 65 by a polymer sealing film 71. This film may be a thermoplastic film such as a PET or Polysulphone film, or it may be in the form of a thermoset film, such as those manufactured by AL technologies and Rogers Corporation. The polymer sealing film 71 is a laminate with adhesive layers on both sides of a central film, and laminated onto the underside of the lower member 65. The holes 72 are laser drilled through the adhesive film 71 to coincide with the centrally disposed ink delivery points (the middle row of holes 69 and the ends of the conduits 70) for fluid communication between the printhead IC 74 and the channels 67.

The thickness of the polymer sealing film 71 is critical to the effectiveness of the ink seal it provides. The polymer sealing film seals the etched channels 77 on the reverse side of the printhead IC 74, as well as the conduits 70 on the other side of the film. However, as the film 71 seals across the open end of the conduits 70, it can also bulge or sag into the conduit. The section of film that sags into a conduit 70 runs across several of the etched channels 77 in the printhead IC 74. The sagging may cause a gap between the walls separating each of the etched channels 77. Obviously, this breaches the seal and allows ink to leak out of the printhead IC 74 and or between etched channels 77.

To guard against this, the polymer sealing film 71 should be thick enough to account for any sagging into the conduits 70 while maintaining the seal over the etched channels 77. The minimum thickness of the polymer sealing film 71 will depend on:

-   -   1. the width of the conduit into which it sags;     -   2. the thickness of the adhesive layers in the film's laminate         structure;     -   3. the ‘stiffness’ of the adhesive layer as the printhead IC 74         is being pushed into it; and,     -   4. the modulus of the central film material of the laminate.

A polymer sealing film 71 thickness of 25 microns is adequate for the printhead assembly 22 shown. However, increasing the thickness to 50, 100 or even 200 microns will correspondingly increase the reliability of the seal provided.

Ink delivery inlets 73 are formed in the ‘front’ surface of a printhead IC 74. The inlets 73 supply ink to respective nozzles 801 (described below with reference to Figures F to J) positioned on the inlets. The ink must be delivered to the IC's so as to supply ink to each and every individual inlet 73. Accordingly, the inlets 73 within an individual printhead IC 74 are physically grouped to reduce ink supply complexity and wiring complexity. They are also grouped logically to minimize power consumption and allow a variety of printing speeds.

Each printhead IC 74 is configured to receive and print five different colors of ink (C, M, Y, K and IR) and contains 1280 ink inlets per color, with these nozzles being divided into even and odd nozzles (640 each). Even and odd nozzles for each color are provided on different rows on the printhead IC 74 and are aligned vertically to perform true 1600 dpi printing, meaning that nozzles 801 are arranged in 10 rows, as clearly shown in FIG. 25. The horizontal distance between two adjacent nozzles 801 on a single row is 31.75 microns, whilst the vertical distance between rows of nozzles is based on the firing order of the nozzles, but rows are typically separated by an exact number of dot lines, plus a fraction of a dot line corresponding to the distance the paper will move between row firing times. Also, the spacing of even and odd rows of nozzles for a given color must be such that they can share an ink channel, as will be described below.

As alluded to previously, the present invention is related to page-width printing and as such the printhead ICs 74 are arranged to extend horizontally across the width of the printhead assembly 22. To achieve this, individual printhead ICs 74 are linked together in abutting arrangement across the surface of the adhesive layer 71. The printhead IC's 74 may be attached to the polymer sealing film 71 by heating the IC's above the melting point of the adhesive layer and then pressing them into the sealing film 71, or melting the adhesive layer under the IC with a laser before pressing them into the film. Another option is to both heat the IC (not above the adhesive melting point) and the adhesive layer, before pressing it into the film 71.

The length of an individual printhead IC 74 is around 20-22 mm. To print an A4/US letter sized page, 11-12 individual printhead ICs 74 are contiguously linked together. The number of individual printhead ICs 74 may be varied to accommodate sheets of other widths.

The printhead ICs 74 may be linked together in a variety of ways. One particular manner for linking the ICs 74 is shown in FIG. 25. In this arrangement, the ICs 74 are shaped at their ends to link together to form a horizontal line of ICs, with no vertical offset between neighboring ICs. A sloping join is provided between the ICs having substantially a 45° angle. The joining edge is not straight and has a sawtooth profile to facilitate positioning, and the ICs 74 are intended to be spaced about 11 microns apart, measured perpendicular to the joining edge. In this arrangement, the left most ink delivery nozzles 73 on each row are dropped by 10 line pitches and arranged in a triangle configuration. This provides a degree of overlap of nozzles at the join and maintains the pitch of the nozzles to ensure that the drops of ink are delivered consistently along the printing zone. It also ensures that more silicon is provided at the edge of the IC 74 to ensure sufficient linkage.

Control of the operation of the nozzles is performed by the SoPEC (SOHO Print Engine Controller). It can compensate for the nozzles in the drop triangle, or this can be performed in the printhead, depending on the storage requirements. It will be appreciated that the dropped triangle arrangement of nozzles disposed at one end of the IC 74 provides the minimum on-printhead storage requirements. However where storage requirements are less critical, shapes other than a triangle can be used, for example, the dropped rows may take the form of a trapezoid.

The upper surface of the printhead ICs have a number of bond pads 75 provided along an edge thereof which provide a means for receiving data and or power to control the operation of the nozzles 73 from the SoPEC device. To aid in positioning the ICs 74 correctly on the surface of the adhesive layer 71 and aligning the ICs 74 such that they correctly align with the holes 72 formed in the adhesive layer 71, fiducials 76 are also provided on the surface of the ICs 74. The fiducials 76 are in the form of markers that are readily identifiable by appropriate positioning equipment to indicate the true position of the IC 74 with respect to a neighboring IC and the surface of the adhesive layer 71, and are strategically positioned at the edges of the ICs 74, and along the length of the adhesive layer 71.

In order to receive the ink from the holes 72 formed in the polymer sealing film 71 and to distribute the ink to the ink inlets 73, the underside of each printhead IC 74 is configured as shown in FIG. 26. A number of etched channels 77 are provided, with each channel 77 in fluid communication with a pair of rows of inlets 73 dedicated to delivering one particular color or type of ink. The channels 77 are about 80 microns wide, which is equivalent to the width of the holes 72 in the polymer sealing film 71, and extend the length of the IC 74. The channels 77 are divided into sections by silicon walls 78. Each sections is directly supplied with ink, to reduce the flow path to the inlets 73 and the likelihood of ink starvation to the individual nozzles 801. Each section feeds approximately 128 nozzles 801 via their respective inlets 73.

The ink is fed to the etched channels 77 formed in the underside of the ICs 74 for supply to the nozzle ink inlets 73. As shown in FIG. 24, holes 72 formed through the polymer sealing film 71 are aligned with one of the channels 77 at the point where the silicon wall 78 separates the channel 77 into sections. The holes 72 are about 80 microns in width which is substantially the same width of the channels 77 such that one hole 72 supplies ink to two sections of the channel 77. This halves the density of holes 72 required in the polymer sealing film 71.

Following attachment and alignment of each of the printhead ICs 74 to the surface of the polymer sealing film 71, a flex PCB 79 (see FIG. 23) is attached along an edge of the ICs 74 so that control signals and power can be supplied to the bond pads 75 to control and operate the nozzles 801. The flex PCB 79 may also have a plurality of decoupling capacitors 81 arranged along its length for controlling the power and data signals received from the control circuitry.

As shown in FIG. 23, a media shield 82 protects the printhead ICs 74 from damage which may occur due to contact with the passing media. The media shield 82 is attached to the upper member 62 upstream of the printhead ICs 74 via an appropriate clip-lock arrangement or via an adhesive. The printhead ICs 74 sit below the surface of the media shield 82, out of the path of the passing media.

A space 83 is provided between the media shield 82 and the upper 62 and lower 65 members which can receive pressurized air from an air compressor or the like. As this space 83 extends along the length of the printhead assembly 22, compressed air can be supplied to either end of the printhead assembly 22 and be evenly distributed along the assembly. The inner surface of the media shield 82 is provided with a series of fins 84 which define a plurality of air outlets evenly distributed along the length of the media shield 82 through which the compressed air travels and is directed across the printhead ICs 74 in the direction of the media delivery. This arrangement acts to prevent dust and other particulate matter carried with the media from settling on the surface of the printhead ICs, which could cause blockage and damage to the nozzles.

9.2 Ink Ejection Nozzles

As discussed above, an array of ink ejection nozzles are formed on the printhead IC 74 over the ink inlets 73. The Applicant has developed many different nozzle structures suitable for this printhead. The fabrication and operation of each of these nozzle types is described in the cross referenced documents listed above. However, two of the more widely adopted nozzle designs are briefly described below.

9.3 Mechanical Bend Actuator

FIGS. 27 to 30 show an ink delivery nozzle 801 formed on a silicon substrate 8015. It will be appreciated that the substrate 8015 equates to the printhead IC 74 (see FIGS. 22 and 26) and a nozzle 801 overlays each of the nozzle ink inlets 73. Each of the nozzle arrangements 801 are identical, however groups of nozzle arrangements 801 are arranged to be fed with different colored inks or fixative. The nozzle arrangements are arranged in rows and are staggered with respect to each other, allowing closer spacing of ink dots during printing than would be possible with a single row of nozzles. Such an arrangement makes it possible to provide a high density of nozzles, for example, more than 5000 nozzles arrayed in a plurality of staggered rows each having an interspacing of about 32 microns between the nozzles in each row and about 80 microns between the adjacent rows. The multiple rows also allow for redundancy (if desired), thereby allowing for a predetermined failure rate per nozzle.

Each nozzle arrangement 801 is the product of an integrated circuit fabrication technique. In particular, the nozzle arrangement 801 defines a micro-electromechanical system (MEMS).

For clarity and ease of description, the construction and operation of a single nozzle arrangement 801 will be described.

The inkjet printhead integrated circuit 74 includes a silicon wafer substrate 8015 having 0.35 micron 1 P4M 12 volt CMOS microprocessing electronics is positioned thereon.

A silicon dioxide (or alternatively glass) layer 8017 is positioned on the substrate 8015. The silicon dioxide layer 8017 defines CMOS dielectric layers. CMOS top-level metal defines a pair of aligned aluminium electrode contact layers 8030 positioned on the silicon dioxide layer 8017. Both the silicon wafer substrate 8015 and the silicon dioxide layer 8017 are etched to define an ink inlet channel 8014 having a generally circular cross section (in plan). An aluminium diffusion barrier 8028 of CMOS metal 1, CMOS metal ⅔ and CMOS top level metal is positioned in the silicon dioxide layer 8017 about the ink inlet channel 8014. The diffusion barrier 8028 serves to inhibit the diffusion of hydroxyl ions through CMOS oxide layers of the drive electronics layer 8017.

A passivation layer in the form of a layer of silicon nitride 8031 is positioned over the aluminium contact layers 8030 and the silicon dioxide layer 8017. Each portion of the passivation layer 8031 positioned over the contact layers 8030 has an opening 8032 defined therein to provide access to the contacts 8030.

The nozzle arrangement 801 includes a nozzle chamber 8029 defined by an annular nozzle wall 8033, which terminates at an upper end in a nozzle roof 8034 and a radially inner nozzle rim 804 that is circular in plan. The ink inlet channel 8014 is in fluid communication with the nozzle chamber 8029. At a lower end of the nozzle wall, there is disposed a moving rim 8010, that includes a moving seal lip 8040. An encircling wall 8038 surrounds the movable nozzle, and includes a stationary seal lip 8039 that, when the nozzle is at rest as shown in FIG. 27, is adjacent the moving rim 8010. A fluidic seal 8011 is formed due to the surface tension of ink trapped between the stationary seal lip 8039 and the moving seal lip 8040. This prevents leakage of ink from the chamber whilst providing a low resistance coupling between the encircling wall 8038 and the nozzle wall 8033.

FIG. 27 also shows a plurality of radially extending recesses in the roof about the nozzle rim 804. These recesses serve to contain radial ink flow as a result of ink escaping past the nozzle rim 804.

The nozzle wall 8033 forms part of a lever arrangement that is mounted to a carrier 8036 having a generally U-shaped profile with a base 8037 attached to the layer 8031 of silicon nitride.

The lever arrangement also includes a lever arm 8018 that extends from the nozzle walls and incorporates a lateral stiffening beam 8022. The lever arm 8018 is attached to a pair of passive beams 806, formed from titanium nitride (TiN) and positioned on either side of the nozzle arrangement. The other ends of the passive beams 806 are attached to the carrier 8036.

The lever arm 8018 is also attached to an actuator beam 807, which is formed from TiN. It will be noted that this attachment to the actuator beam is made at a point a small but critical distance higher than the attachments to the passive beam 806.

The actuator beam 807 is substantially U-shaped in plan, defining a current path between the electrode 809 and an opposite electrode 8041. Each of the electrodes 809 and 8041 are electrically connected to respective points in the contact layer 8030. As well as being electrically coupled via the contacts 809, the actuator beam is also mechanically anchored to anchor 808. The anchor 808 is configured to constrain motion of the actuator beam 807 to the left of FIG. 27 when the nozzle arrangement is in operation.

The TiN in the actuator beam 807 is conductive, but has a high enough electrical resistance that it undergoes self-heating when a current is passed between the electrodes 809 and 8041. No current flows through the passive beams 806, so they do not expand.

In use, the device at rest is filled with ink 8013 that defines a meniscus 803 under the influence of surface tension. The ink is retained in the chamber 8029 by the meniscus, and will not generally leak out in the absence of some other physical influence.

As shown in FIG. 29, to fire ink from the nozzle, a current is passed between the contacts 809 and 8041, passing through the actuator beam 807. The self-heating of the beam 807 due to its resistance causes the beam to expand. The dimensions and design of the actuator beam 807 mean that the majority of the expansion in a horizontal direction with respect to FIGS. 28 to 30. The expansion is constrained to the left by the anchor 808, so the end of the actuator beam 807 adjacent the lever arm 8018 is impelled to the right.

The relative horizontal inflexibility of the passive beams 806 prevents them from allowing much horizontal movement the lever arm 8018. However, the relative displacement of the attachment points of the passive beams and actuator beam respectively to the lever arm causes a twisting movement that causes the lever arm 8018 to move generally downwards. The movement is effectively a pivoting or hinging motion. However, the absence of a true pivot point means that the rotation is about a pivot region defined by bending of the passive beams 806.

The downward movement (and slight rotation) of the lever arm 8018 is amplified by the distance of the nozzle wall 8033 from the passive beams 806. The downward movement of the nozzle walls and roof causes a pressure increase within the chamber 8029, causing the meniscus to bulge as shown in FIG. 29. It will be noted that the surface tension of the ink means the fluid seal 8011 is stretched by this motion without allowing ink to leak out.

As shown in FIG. 30, at the appropriate time, the drive current is stopped and the actuator beam 807 quickly cools and contracts. The contraction causes the lever arm to commence its return to the quiescent position, which in turn causes a reduction in pressure in the chamber 8029. The interplay of the momentum of the bulging ink and its inherent surface tension, and the negative pressure caused by the upward movement of the nozzle chamber 8029 causes thinning, and ultimately snapping, of the bulging meniscus to define an ink drop 802 that continues upwards until it contacts adjacent print media.

Immediately after the drop 802 detaches, meniscus 803 forms the concave shape shown in FIG. 30. Surface tension causes the pressure in the chamber 8029 to remain relatively low until ink has been sucked upwards through the inlet 8014, which returns the nozzle arrangement and the ink to the quiescent situation shown in Fig. G.

9.4 Thermal Bubble Actuator

Another type of printhead nozzle arrangement suitable for the present invention will now be described with reference to FIG. 31. Once again, for clarity and ease of description, the construction and operation of a single nozzle arrangement 1001 will be described.

The nozzle arrangement 1001 is of a bubble forming heater element actuator type which comprises a nozzle plate 1002 with a nozzle 1003 therein, the nozzle having a nozzle rim 1004, and aperture 1005 extending through the nozzle plate. The nozzle plate 1002 is plasma etched from a silicon nitride structure which is deposited, by way of chemical vapor deposition (CVD), over a sacrificial material which is subsequently etched.

The nozzle arrangement includes, with respect to each nozzle 1003, side walls 1006 on which the nozzle plate is supported, a chamber 1007 defined by the walls and the nozzle plate 1002, a multi-layer substrate 1008 and an inlet passage 1009 extending through the multi-layer substrate to the far side (not shown) of the substrate. A looped, elongate heater element 1010 is suspended within the chamber 1007, so that the element is in the form of a suspended beam. The nozzle arrangement as shown is a microelectromechanical system (MEMS) structure, which is formed by a lithographic process.

When the nozzle arrangement is in use, ink 1011 from a reservoir (not shown) enters the chamber 1007 via the inlet passage 1009, so that the chamber fills. Thereafter, the heater element 1010 is heated for somewhat less than 1 micro second, so that the heating is in the form of a thermal pulse. It will be appreciated that the heater element 1010 is in thermal contact with the ink 1011 in the chamber 1007 so that when the element is heated, this causes the generation of vapor bubbles in the ink. Accordingly, the ink 1011 constitutes a bubble forming liquid.

The bubble 1012, once generated, causes an increase in pressure within the chamber 1007, which in turn causes the ejection of a drop 1016 of the ink 1011 through the nozzle 1003. The rim 1004 assists in directing the drop 1016 as it is ejected, so as to minimize the chance of drop misdirection.

The reason that there is only one nozzle 1003 and chamber 1007 per inlet passage 1009 is so that the pressure wave generated within the chamber, on heating of the element 1010 and forming of a bubble 1012, does not affect adjacent chambers and their corresponding nozzles.

The increase in pressure within the chamber 1007 not only pushes ink 1011 out through the nozzle 1003, but also pushes some ink back through the inlet passage 1009. However, the inlet passage 1009 is approximately 200 to 300 microns in length, and is only approximately 16 microns in diameter. Hence there is a substantial viscous drag. As a result, the predominant effect of the pressure rise in the chamber 1007 is to force ink out through the nozzle 1003 as an ejected drop 1016, rather than back through the inlet passage 1009.

As shown in FIG. 31, the ink drop 1016 is being ejected is shown during its “necking phase” before the drop breaks off. At this stage, the bubble 1012 has already reached its maximum size and has then begun to collapse towards the point of collapse 1017.

The collapsing of the bubble 1012 towards the point of collapse 1017 causes some ink 1011 to be drawn from within the nozzle 1003 (from the sides 1018 of the drop), and some to be drawn from the inlet passage 1009, towards the point of collapse. Most of the ink 1011 drawn in this manner is drawn from the nozzle 1003, forming an annular neck 1019 at the base of the drop 1016 prior to its breaking off.

The drop 1016 requires a certain amount of momentum to overcome surface tension forces, in order to break off. As ink 1011 is drawn from the nozzle 1003 by the collapse of the bubble 1012, the diameter of the neck 1019 reduces thereby reducing the amount of total surface tension holding the drop, so that the momentum of the drop as it is ejected out of the nozzle is sufficient to allow the drop to break off.

When the drop 1016 breaks off, cavitation forces are caused as reflected by the arrows 1020, as the bubble 1012 collapses to the point of collapse 1017. It will be noted that there are no solid surfaces in the vicinity of the point of collapse 1017 on which the cavitation can have an effect.

9.5 Control Circuitry

The printhead integrated circuits 74 (see FIG. 22) may have between 5000 to 100,000 of the above described ink delivery nozzles arranged along its surface, depending upon the length of the integrated circuits and the desired printing properties required. For example, for narrow media it may be possible to only require 5000 nozzles arranged along the surface of the printhead assembly to achieve a desired printing result, whereas for wider media a minimum of 10,000, 20,000 or 50,000 nozzles may need to be provided along the length of the printhead assembly to achieve the desired printing result. For full color photo quality images on A4 or US letter sized media at or around 1600 dpi, the integrated circuits 74 may have 13824 nozzles per color. In the case where the printhead assembly 22 is capable of printing in 4 colours (C, M, Y, K), the integrated circuits 74 may have around 53396 nozzles disposed along the surface thereof. Similarly, if the printhead assembly 22 is capable of printing 6 printing fluids (C, M, Y, K, IR and a fixative) this may result in 82944 nozzles being provided on the surface of the integrated circuits 74. In all such arrangements, the electronics supporting each nozzle is the same.

The manner in which the individual ink delivery nozzle arrangements may be controlled within the printhead assembly 22 will now be described with reference to FIGS. 32 to 34.

FIG. 32 shows an overview of the integrated circuit 74 and its connections to the print engine controller (PEC) provided within the control electronics of the print engine 1. As discussed above, integrated circuit 74 includes a nozzle core array 901 containing the repeated logic to fire each nozzle, and nozzle control logic 902 to generate the timing signals to fire the nozzles. The nozzle control logic 902 receives data from the PEC 903 via a high-speed link.

The nozzle control logic 902 is configured to send serial data to the nozzle array core for printing, via a link 907, which may be in the form of an electrical connector. Status and other operational information about the nozzle array core 901 is communicated back to the nozzle control logic 902 via another link 908, which may be also provided on the electrical connector.

The nozzle array core 901 is shown in more detail in FIGS. 33 and 34. In FIG. 33, it will be seen that the nozzle array core 901 comprises an array of nozzle columns 911. The array includes a fire/select shift register 912 and up to 6 color channels, each of which is represented by a corresponding dot shift register 913.

As shown in FIG. 34, the fire/select shift register 912 includes forward path fire shift register 930, a reverse path fire shift register 931 and a select shift register 932. Each dot shift register 913 includes an odd dot shift register 933 and an even dot shift register 934. The odd and even dot shift registers 933 and 934 are connected at one end such that data is clocked through the odd shift register 933 in one direction, then through the even shift register 934 in the reverse direction. The output of all but the final even dot shift register is fed to one input of a multiplexer 935. This input of the multiplexer is selected by a signal (corescan) during post-production testing. In normal operation, the corescan signal selects dot data input Dot[x] supplied to the other input of the multiplexer 935. This causes Dot[x] for each color to be supplied to the respective dot shift registers 913 (see FIG. 33).

A single column N will now be described with reference to FIG. 35. In the embodiment shown, the column N includes 12 data values, comprising an odd data value 936 and an even data value 937 for each of the six dot shift registers. Column N also includes an odd fire value 938 from the forward fire shift register 930 and an even fire value 939 from the reverse fire shift register 931, which are supplied as inputs to a multiplexer 940. The output of the multiplexer 940 is controlled by the select value 941 in the select shift register 932. When the select value is zero, the odd fire value is output, and when the select value is one, the even fire value is output.

Each of the odd and even data values 936 and 937 is provided as an input to corresponding odd and even dot latches 942 and 943 respectively.

Each dot latch and its associated data value form a unit cell. The details of a unit cell 944 is shown in more detail in FIG. 35. The dot latch 942 is a D-type flip-flop that accepts the output of the data value 936, which is held by a D-type flip-flop 946 forming an element of the odd dot shift register 933 (see FIG. 34). The data input to the flip-flop 946 is provided from the output of a previous element in the odd dot shift register (unless the element under consideration is the first element in the shift register, in which case its input is the Dot[x] value). Data is clocked from the output of flip-flop 946 into latch 942 upon receipt of a negative pulse provided on LsyncL.

The output of latch 942 is provided as one of the inputs to a three-input AND gate 945. Other inputs to the AND gate 945 are the Fr signal (from the output of multiplexer 940 (see FIG. 34)) and a pulse profile signal Pr. The firing time of a nozzle is controlled by the pulse profile signal Pr, and can be, for example, lengthened to take into account a low voltage condition that arises due to low power supply (in a removable power supply (battery) embodiment). This is to ensure that a relatively consistent amount of ink is efficiently ejected from each nozzle as it is fired. In the embodiment described, the profile signal Pr is the same for each dot shift register, which provides a balance between complexity, cost and performance. However, in other embodiments, the Pr signal can be applied globally (ie, is the same for all nozzles), or can be individually tailored to each unit cell or even to each nozzle.

Once the data is loaded into the latch 942, the fire enable Fr and pulse profile Pr signals are applied to the AND gate 945, combining to the trigger the nozzle to eject a dot of ink for each latch 942 that contains a logic 1.

The signals for each nozzle channel are summarized in the following table:

Name Direction Description D Input Input dot pattern to shift register bit Q Output Output dot pattern from shift register bit SrClk Input Shift register clock in - d is captured on rising edge of this clock LsyncL Input Fire enable - needs to be asserted for nozzle to fire Pr Input Profile - needs to be asserted for nozzle to fire

As shown in FIG. 35, the fire signals Fr are routed on a diagonal, to enable firing of one color in the current column, the next color in the following column, and so on. This averages the current demand by spreading it over 6 columns in time-delayed fashion.

The dot latches and the latches forming the various shift registers are fully static in this embodiment, and are CMOS-based. The design and construction of latches is well known to those skilled in the art of integrated circuit engineering and design, and so will not be described in detail in this document.

The nozzle speed may be as much as 20 kHz for the printer capable of printing at about 60 ppm, and even more for higher speeds. At this range of nozzle speeds the amount of ink than can be ejected by the entire printhead assembly (see FIG. 22) is at least 50 million drops per second. However, as the number of nozzles is increased to provide for higher-speed and higher-quality printing at least 100 million drops per second, preferably at least 500 million drops per second and more preferably at least 1 billion drops per second may be delivered. At such speeds, the drops of ink are ejected by the nozzles with a maximum drop ejection energy of about 250 nanojoules per drop.

Consequently, in order to accommodate printing at these speeds, the control electronics must be able to determine whether a nozzle is to eject a drop of ink at an equivalent rate. In this regard, in some instances the control electronics must be able to determine whether a nozzle ejects a drop of ink at a rate of at least 50 million determinations per second. This may increase to at least 100 million determinations per second or at least 500 million determinations per second, and in many cases at least 1 billion determinations per second for the higher-speed, higher-quality printing applications.

The number of nozzles provided on the printhead assembly together with the nozzle firing speeds and print speeds, results in an area print speed of at least 50 cm2 per second, and depending on the printing speed, at least 100 cm2 per second, preferably at least 200 cm2 per second, and more preferably at least 500 cm2 per second at the higher-speeds. Such an arrangement provides a printer that is capable of printing a given area of media at speeds not previously attainable with conventional printers.

10. Decoder Architecture

A desire to minimise clock speed and power consumption motivates a dedicated decoder design. Conversely, a desire to minimise complexity motivates an ALU-based decoder design. Various compromises between these two extremes exist, such as a hybrid design which includes both an ALU and dedicated blocks.

An ALU-based decoder can also be used to implement a single-chip product, i.e. in the absence of an additional host controller, with the ALU executing product application software as well as reader and decoder software. Alternatively the decoder is included as a block in a larger application-specific integrated circuit (ASIC) or system-on-a-chip (SoC). This is discussed in Section 10.2.

EQ 116 gives the rate r_(d) at which the decoder interpolates and resolves bit values. Since the decoder processes every scanline, the rate r_(d)′ at which it generates candidate encoding locations is higher than r_(d) by a factor N:

$\begin{matrix} {r_{d}^{\prime} = {{r_{d}N} = \frac{{\overset{\sim}{r}}_{s}}{N}}} & \left( {{EQ}\mspace{14mu} 126} \right) \end{matrix}$

The two most demanding tasks performed by the decoder are clock tracking and data decoding. Data decoding is relatively simple, but must be performed at the average data rates r_(d) and r_(d)′ described above. Clock tracking is more complex, but because it is spatially localised it can be amortised over the line time corresponding to the block width. A higher clock rate can obviously be used alternatively or additionally to amortising clock tracking over the block width.

Because expected clock variation is of low frequency, data clock PLLs can be used predictively to provide clock estimates for a given scanline, even while the PLLs are being updated for that scanline.

Assuming no data parallelism, r_(d)′ therefore defines a minimum value for the clock speed r_(c) of a dedicated decoder:

r_(c)≧r_(d)′  (EQ 127)

The minimum clock speed of an ALU-based decoder is higher still, and is a function of its instruction set and how many dedicated blocks it incorporates.

Since an ALU-based decoder trivially implements the decoding algorithm in software, the remainder of this section describes a dedicated decoder design. Blocks of this dedicated decoder design can be used to produce a hybrid design.

FIG. 36 shows a high-level block diagram of the decoder 714 in the context of the Mnem reader. It consists of a controller 720, a raw decoder 721, and a redundancy decoder 722. The controller controls the external peripherals in synchrony with the raw decoder during the first raw decoding phase, and controls the redundancy decoder during the optional second redundancy decoding phase.

During the scan the controller generates the line clock, and from the line clock derives the control signals which control the illumination LEDs 710, the image sensor 711, and the transport motor 713 via the general-purpose I/O interface GPIO 723, as well as the internal raw decoder 721.

The decoder 721 acquires pixel-wide (i.e. typically 8-bit wide) samples from the image sensor 711, via an image sensor interface 724 into an input line buffer 725 at the image sensor read-out rate r_(i). The decoder maintains three input line buffers, and alternates between them on successive lines. On any given line, one buffer is being written to from the image sensor interface 724, and two buffers are being read by the raw decoder 721. Due to the read-out considerations discussed in Section 7.3, the image sensor read-out rate r_(i) is generally higher than the average scan data rate {tilde over (r)}_(s), which in turn is higher than the decoder clock speed r_(c) by a factor N or less (see EQ 126 and EQ 127).

During the scan the raw decoder 721 decodes scan data line by line, and writes decoded raw data to external memory 715, via a memory interface 726.

If the decoder is configured to perform redundancy decoding, then after the scan is complete the controller signals the redundancy decoder 722 to perform redundancy decoding. The redundancy decoder reads raw data from external memory 715 and writes corrected data back to external memory.

If the decoder is configured to interrupt the host controller on completion, then after decoding is complete the controller signals the host controller via an interrupt interface 727.

The decoder provides the host controller with read-write access to configuration registers 728 and read access to status registers 728 via a serial interface 729.

FIG. 37 shows a high-level block diagram of the raw decoder. It contains a block decoder 730 which implements the state machine described in Section 3.1. As the block processes a scanline, it indexes the block state 731 in internal memory associated with each block column in turn.

The block decoder 730 uses a shared PLL 732 to acquire the pilot and acquire and track the registration clocks. It uses a clock decoder 733 to track the data clocks and their associated alignment lines. It uses a data decoder 736 to generate candidate encoding locations and to interpolate and threshold unresolved bit values. It uses a bit resolver 739 to generate resolved bit values from unresolved bit values. It uses a column flusher 740 to flush resolved raw data words to external memory 715.

The clock decoder 733 implements the data clock tracking algorithm described in Section 4. It indexes the clock state 734 in internal memory associated with the current data clock within the current block. The clock decoder uses a transform generator 735 to generate the block space to scan space transform based on the two data clocks.

The PLL 732 is shared and multi-purpose. It implements a digital PLL as described in Section 6. It operates on the PLL state of the appropriate clock, maintained as part of the current block state 731 or current clock state 734.

The data decoder 736 implements the unresolved bit decoding algorithm described in Section 3.1.3. It indexes the column state 737 in internal memory associated with the current column within the current block, and writes unresolved bit values to the current column within the output buffer 738 associated with the current block, pending resolution and flushing to external memory. The data decoder 736 uses the block space to scan space transform generated by the transform generator 735 to generate the coordinates of successive candidate bit encoding locations.

The transform generator 735 implements the algorithm described in Section 5.

The bit resolver 739 implements the bit resolution algorithm described in Section 3.1.3. It resolves bit values within the column previous to the current column within the output buffer associated with the current block

The column flusher 740 uses an address generator 741 to generate the output address for each data column, as described in Section 3.1.3. If redundancy decoding is enabled, then the column flusher writes bitstream parameter column data to a separate external memory area.

FIG. 38 shows a high-level block diagram of the redundancy decoder. It contains a parameter decoder 750 which extracts bitstream parameters from the CRC-encoded parameter data, and a bitstream decoder 752 which corrects errors in the raw data via the Reed-Solomon redundancy data associated with the raw data.

The parameter decoder 750 implements the algorithm described in Section 3.2.1. It reads CRC-encoded bitstream parameter data from external memory 715 via the memory interface 726. It uses a CRC generator 751 to generate CRCs to allow it to detect valid parameter data.

Once the parameter decoder 750 obtains valid bitstream parameters, it signals the bitstream decoder 752 to correct errors in the raw data. The bitstream decoder 752 implements the algorithm described in Section 3.2.2. It uses a codeword interleaver 754 to interleave, during read-out from external memory 715, the distributed raw data of each codeword and its associated redundancy data; a Reed-Solomon decoder 753 to correct errors in the codeword; and a codeword de-interleaver 756 to write corrected raw data back to its distributed locations.

The interleaver 754 and de-interleaver 756 share an address generator 755, which generates the distributed byte addresses of codeword symbols.

The decoder may utilise off-the-shelf functional blocks as required. For example, Reed-Solomon decoder blocks which support CCSDS codes are widely available, such as Xilinx, Reed-Solomon Decoder V3.0, 14 Mar. 2002.

10.1 Internal Memory Estimates

The decoder uses three scanline buffers to buffer image sensor input. Assuming 8-bit samples, the size z_(i) of each scan buffer is given by:

z_(i)=8{tilde over (W)}_(s)  (EQ 128)

The decoder uses a word-width output buffer per data column to buffer resolved output bits pending word-width writes to external memory. Assuming an output word size of w bits, the size z₀ of the output buffer is approximately given by:

z₀=wW_(m)  (EQ 129)

The decoder also buffers two unresolved bit values, each represented by a two-bit value, per data column.

The total size z_(t) of the decoder's internal memory, ignoring block state, is therefore given by:

{tilde over (z)} _(t)=8{tilde over (W)}_(s)+(w+2)W _(m)  (EQ 130)

10.2 Decoder Configuration

The decoder may be configured as a stand-alone ASIC or it may be included as a block in a larger ASIC or SoC.

As mentioned earlier, the decoder may be dynamically configured via its registers to decode a variety of Mnem configurations. The decoding parameters may also be statically configured with suitable default values.

Although the design of the decoder is scalable in terms of media size and shape, decoding time, clock speed and power consumption, the capabilities of a particular decoder implementation are limited by its maximum clock speed and the size of its internal buffers.

To be designed as a re-usable block, the decoder's internal buffer memory is best separated from the decoder itself so that the decoder is easily re-used with different buffer memory sizes.

11. Sample Mnem Configurations 11.1 3.5″×2.5″ Playing Card

TABLE 4 Variable parameters parameter Value description α_(max) 2 degrees Maximum α, the rotation of the block in scan space. Δ_(b) 0 The nominal edge-to-edge spacing between adjacent blocks, and twice the maximum block misalignment. Δ_(m) 100 1 mm rounded up to 100 dots The nominal minimum x spacing between the edge of the Mnem area and the edge of the scan, and the maximum horizontal Mnem area misalignment. H_(b) _(max) 1080 The maximum height of a block. H_(m) 5400 ¹3.5″ less 0.05″ border rounded up to 100 dots The height of the Mnem area. N 3 The sampling rate, i.e. the nominal block space to scan space scale factor. R 1600/inch The real space to Mnem space scale factor. W_(b) _(max) 760 The maximum width of a block. W_(m) 3800 2.5″ less 0.05″ border rounded up to 100 dots The width of the Mnem area. v_(r) 2 inches/s The transport speed. w 16 The width of external memory writes.

11.2 Printed Using Memjet

TABLE 5 Selected derived parameters parameter equation value description Δ_(f) EQ 7 120 The edge-to-edge spacing between adjacent registration markers. D_(m) EQ 15 2.1 MB The raw capacity of the Mnem area. E_(m) EQ 23 1.8 MB The encoded capacity of the Mnem area. H_(b) EQ 16 1073 The height of the block. H_(d) EQ 13 944 The height of the data grid (always a multiple of 8). H_(h) EQ 11 129 The height of the block overhead. H_(r) EQ 8 21 The height of the registration track. m EQ 1 5 The number of block rows in the Mnem area. n EQ 2 5 The number of block columns in the Mnem area. W_(b) EQ 4 760 The width of the block. W_(d) EQ 14 742 The width of the data grid. W_(f) EQ 6 120 The width of a registration marker. W_(h) EQ 12 18 The width of the block overhead. W_(p) EQ 21 758 The width of the pilot. W_(r) EQ 22 540 The width of the registration track. {tilde over (W)}_(s) EQ 24 13130 The width of a scanline. W_(w) EQ 10 108 The width of the wide data clock track. r_(c) EQ 127 12 MHz The decoder clock speed. z_(t) EQ 130 21 KB Internal memory requirements.

11.3 6″×4″ Photo

TABLE 6 Variable parameters parameter value description α_(max) 2 degrees Maximum α, the rotation of the block in scan space. Δ_(b) 0 The nominal edge-to-edge spacing between adjacent blocks, and twice the maximum block misalignment. Δ_(m) 100 1 mm rounded up to 100 dots The nominal minimum x spacing between the edge of the Mnem area and the edge of the scan, and the maximum horizontal Mnem area misalignment. H_(b) _(max) 1175 The maximum height of a block. H_(m) 9400 6″ less 0.05″ border rounded up to 100 dots The height of the Mnem area. N 3 The sampling rate, i.e. the nominal block space to scan space scale factor. R 1600/inch The real space to Mnem space scale factor. W_(b) _(max) 775 The maximum width of a block. W_(m) 6200 4″ less 0.05″ border rounded up to 100 dots The width of the Mnem area. v_(r) 2 inches/s The transport speed. w 16 The width of external memory writes.

11.4 Printed Using Memjet

TABLE 7 Selected derived parameters parameter equation value description Δ_(f) EQ 7 120 The edge-to-edge spacing between adjacent registration markers. D_(m) EQ 15 6.0 MB The raw capacity of the Mnem area. E_(m) EQ 23 5.2 MB The encoded capacity of the Mnem area. H_(b) EQ 16 1173 The height of the block. H_(d) EQ 13 1040 The height of the data grid (always a multiple of 8). H_(h) EQ 11 133 The height of the block overhead. H_(r) EQ 8 23 The height of the registration track. m EQ 1 8 The number of block rows in the Mnem area. n EQ 2 8 The number of block columns in the Mnem area. W_(b) EQ 4 775 The width of the block. W_(c) EQ 9 7 The width of the data clock track. W_(d) EQ 14 757 The width of the data grid. W_(f) EQ 6 120 The width of a registration marker. W_(h) EQ 12 18 The width of the block overhead. W_(p) EQ 21 773 The width of the pilot. W_(r) EQ 22 555 The width of the registration track. {tilde over (W)}_(s) EQ 24 21170 The width of a scanline. W_(w) EQ 10 108 The width of the wide data clock track. r_(c) EQ 127 20 MHz The (minimum) decoder clock speed. z_(t) EQ 130 35 KB Internal memory requirements.

12. Effect of Blur on Bit-Encoding Value

FIG. 39 shows an empty bit-encoding location whose eight surrounding bit-encoding locations are all marked. The mark diameter shown is the maximum allowed. This arrangement yields the worst-case effect of neighbouring marks on the imaged grayscale value of the central bit-encoding location.

The marks in FIG. 39 are not blurred. The effect of blur is explored in subsequent figures.

FIG. 40 shows a histogram of the imaged grayscale value of the central bit-encoding location for all possible neighbouring mark arrangements, and in the absence of blur, for both a central mark (black bar) and a central hole (gray bars).

For the purpose of computing the histogram, block space is supersampled at 23:1. The imaged grayscale value is computed by averaging the supersampled image within a block-space unit square centred on the central bit-encoding location. Blur is computed using a low-pass box filter.

FIG. 41 and FIG. 43 show the arrangement of FIG. 20 with increasing amounts of blur. FIG. 42 and FIG. 44 show histograms of the imaged grayscale value of the central bit-encoding location for all possible neighbouring mark arrangements, computed with corresponding amounts of blur.

As shown in the histograms, as image blur increases the separation between the range of possible values representing a mark and the range of possible values representing a hole decreases to zero.

The five distinct modes in the hole intensity distributions correspond to the five possible combinations of marks at the bit-encoding locations directly adjacent to the central bit-encoding location. Marks at the diagonally-adjacent bit-encoding locations have a much smaller effect.

13. Relation to Earlier DotCard Design 13.1 Raw Data Layer

The Mnem raw data layer decouples block detection and y registration from block x registration, using a pilot sequence for block detection and y registration, and a multi-resolution registration track for x registration. In comparison with dotCard's two-dimensional targets, this approach simplifies decoding and is more redundant and robust.

13.2 Fault-Tolerant Layer

The Mnem fault-tolerant layer uses CRCs on replicated bitstream parameter data to allow parameter decoding before Reed-Solomon decoding. This allows optimal interleaving of variable-length bitstreams, and allows in situ Reed-Solomon decoding (see below).

The Mnem fault-tolerant layer uses significantly less Reed-Solomon redundancy (15% versus 50%) than dotCard. This increases data density and simplifies decoding.

13.3 Decoding Algorithm

The Mnem decoding algorithm differs from the dotCard decoding algorithm in several ways, all of which are also applicable to dotCard decoding.

The Mnem algorithm uses scanline decoding rather printline decoding. Scanline decoding extracts data by traversing a scanline, while printline decoding extracts data by traversing a printline, i.e. by visiting all of the scanlines the printline intersects. Scanline decoding allows the Mnem algorithm to operate without off-chip buffering for raw scan data, significantly reducing external memory requirements and memory bandwidth.

Printline decoding requires an amount of external memory proportional to the maximum rotation of the block (for small angles) and the square of the media width (this can be reduced to the square of the block width with some additional decoding complexity). For the media width of 2.2 inches and maximum block rotation of 1 degree assumed in the original dotCard study, the design of which has been disclosed in a series of Granted patents and pending patent applications listed in the cross references above, printline decoding requires about 2 MB of temporary scan memory. For a media width of 4 inches printline decoding requires about 6.7 MB of temporary scan memory. Note that scanline decoding assumes a constant print speed, while printline decoding assumes a constant scan speed.

The Mnem algorithm uses a conventional PLL. This is both less complex and less susceptible to noise than the dotCard algorithm's ad hoc PLL, which has an inefficient phase detector and lacks a proper loop filter.

The Mnem algorithm uses the full local context for bit value disambiguation. This improves accuracy and partially makes up for reduced Reed-Solomon redundancy.

The Mnem algorithm uses on-the-fly interleaving and de-interleaving of redundancy-encoded data to allow in-situ decoding. This ensures contiguity of decoded data, simplifying its use by applications. Pre- and post-process interleaving and de-interleaving can only be performed in situ if the interleave factor equals the codeword size. 

1. A system for decoding coded data printed in ink on a surface, the coded data having a registration structure, the registration structure having at least two clock tracks indicative of a position of the coded data in the direction perpendicular to an alignment direction and two alignment lines for each clock track, the two alignment lines being indicative of the position of the respective clock track, the system comprising a decoder for: determining, using an alignment phase-locked loop (PLL), a position of the alignment lines for a respective clock track; determining, using the position of the alignment lines, the position of each respective track; and updating the alignment PLL.
 2. A system according to claim 1, wherein the decoder is for decoding the coded data by: determining a transform for each scan line using the alignment data, the transform being indicative of coordinates of bit-encoding locations within the data portions; and, detecting bit values using the transform.
 3. A system according to claim 2, wherein the decoder is for: determining coordinates of sample values from the coordinates of the bit-encoding location; and, determining a bit-encoding value by interpolating sample values from two successive sample lines.
 4. A system according to claim 1, wherein the decoder is for: determining the position of at least one marker to determine a gross registration; determining, using the gross registration, a clock indicator in a clock track; updating, using the clock indicator, an alignment PLL; determining, using the alignment PLL, a fine registration of the coded data in the alignment direction.
 5. A system according to claim 1, wherein the decoder is for: for each clock track, determining, using a respective data clock PLL, a position of a clock indicator on the clock track; determining, using the position of the clock indicator on each clock track, an alignment angle; and, updating each data clock PLL. 